MPH-02, MPB-02, MPD-02
Master Communication
4-9
DOK-INDRV*-MP*-02VRS**-FK01-EN-P
Timing Diagrams for Device Control
Note:
The control bits in parameter S-0-0134, Master control word
are input externally via the master communication (the
following examples are valid for SERCOS)!
DK000057v01_en.fh7
t
P-0-0115, bit 14
ready for operation
S-0-0134, bit 15
drive ON
S-0-0134, bit 14
drive enable
S-0-0206
P-0-0115, bit 15
ready for operation
P-0-0115, bit 3
status of
cmd. value processing
P-0-0115, bit 7
operating mode
initialized
output stage active
S-0-0206:
drive on delay time
Fig. 4-8:
Bit sequence during switch-on process
standstill; apply holding brake
S-0-0207
DK000058v01_en.fh7
t
P-0-0115, bit 14
ready for operation
S-0-0134, bit 15
drive ON
S-0-0134, bit 14
drive enable
P-0-0115, bit 15
ready for operation
P-0-0115, bit 3
status of
cmd. value processing
P-0-0115, bit 7
operating mode
initialized
n
act
= 0
S-0-0207:
drive off delay time
Fig. 4-9:
Bit sequence during switch-off process
Bit Sequence During Switch-On
Process
Bit Sequence During Switch-Off
Process
Courtesy
of
CMA/Flodyne/Hydradyne
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Control
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