Appendix B Internal I/O Registers
Rev.3.00 Jul. 19, 2007 page 482 of 532
REJ09B0397-0300
RDR—Receive data register
H'AD
SCI3
Bit
Initial value
Read/Write
7
RDR7
0
R
6
RDR6
0
R
5
RDR5
0
R
4
RDR4
0
R
3
RDR3
0
R
0
RDR0
0
R
2
RDR2
0
R
1
RDR1
0
R
TMA—Timer mode register A
H'B0
Timer A
Bit
Initial value
Read/Write
7
TMA7
0
R/W
6
TMA6
0
R/W
5
TMA5
0
R/W
0
TMA0
0
R/W
2
TMA2
0
R/W
1
TMA1
0
R/W
Internal clock select
TMA3 TMA2
0
PSS
PSS
PSS
PSS
0
4
—
1
—
Clock output select
0
φ
/32
φ
/16
TMA1
0
1
TMA0
0
0
1
1
PSS
PSS
PSS
PSS
1
0
1
0
0
1
1
1
PSW
PSW
PSW
PSW
0
0
1
0
0
1
1
PSW and TCA are reset
1
0
1
0
0
1
1
Prescaler and Divider Ratio
or Overflow Period
φ
/8192
φ
/4096
φ
/2048
φ
/512
φ
/256
φ
/128
φ
/32
φ
/8
1 s
0.5 s
0.25 s
0.03125 s
Interval
timer
Time
base
Function
0 0
1
φ
/8
φ
/4
1 0
1
1 0 0
1
1 0
1
φ
/32
W
φ
/16
W
φ
/8
W
φ
/4
W
3
TMA3
0
R/W
Summary of Contents for F-ZTAT H8 Series
Page 6: ...Rev 3 00 Jul 19 2007 page iv of xxiv REJ09B0397 0300...
Page 194: ...7 RAM Rev 3 00 Jul 19 2007 page 168 of 532 REJ09B0397 0300...
Page 234: ...8 I O Ports Rev 3 00 Jul 19 2007 page 208 of 532 REJ09B0397 0300...
Page 274: ...9 Timers Rev 3 00 Jul 19 2007 page 248 of 532 REJ09B0397 0300...
Page 352: ...12 A D Converter Rev 3 00 Jul 19 2007 page 326 of 532 REJ09B0397 0300...
Page 561: ......
