Renesas F-ZTAT H8 Series, Hardware Manual

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6. ROM
Rev.3.00 Jul. 19, 2007 page 147 of 532
REJ09B0397-0300
3. When a SLEEP instruction (including software standby) is executed during
programming/erasing
Error protection is released only by a reset.
Figure 6.14 shows the flash memory state transition diagram.
Notes: 1. This is the state in which the P bit or E bit is set to 1 in FLMCR1.
2. FLMCR1, FLMCR2, and EBR can be written to. However, registers will be initialized
if a transition is made to software standby mode in the error protection state.
3. The read value is undefined.
4. Before exception handling stack and vector read operations are performed.
: Memory read possible
: Verify-read possible
: Pro
g rammin g possible
: Erasin g possible
RD
VF
PR
ER : Memory read not possible
: Verify-read not possible
: Pro
g rammin g not possible
: Erasin g not possible
: Re g ister (FLMCR1, FLMCR2, EBR) initialization state
RD
VF
PR
ER
INIT
RD VF
PR ER FLER = 0
Error
occurrence
Error occurre
nce
(software standby)
RES
= 0
RES
= 0
RES
= 0
RD VF PR ER
FLER = 0
Pro g ram mode
Erase mode
Reset
(hardware protection)
RD VF
PR ER
FLER = 1
RD VF PR ER
INIT
FLER = 1
Error protect mode
Error protect mode
(standby mode)
Standby mode
FLMCR1, FLMCR2 (except FLER bit),
and EBR initialized
FLMCR1, FLMCR2,
and EBR initialized
Standby mode release
Le g end:
Figure 6.14 Flash Memory State Transitions
The error protection function is invalid for abnormal operations other than the FLER bit setting
conditions. Also, if a certain time has elapsed before this protection state is entered, damage may
already have been caused to the flash memory. Consequently, this function cannot provide
complete protection against damage to flash memory.