5. Power-Down Modes
Rev.3.00 Jul. 19, 2007 page 105 of 532
REJ09B0397-0300
Bits 6 to 4—Standby Timer Select 2 to 0 (STS2 to STS0):
These bits designate the time the
CPU and peripheral modules wait for stable clock operation after exiting from standby mode or
watch mode to active mode due to an interrupt. The designation should be made according to the
clock frequency so that the waiting time is at least 10 ms.
Bit 6: STS2 Bit 5: STS1 Bit 4: STS0 Description
0
0
0
Wait time = 8,192 states
(initial value)
1
Wait time = 16,384 states
1
0
Wait time = 32,768 states
1
Wait time = 65,536 states
1
*
*
Wait time = 131,072 states
Legend:
*
Don't care
Bit 3—Low Speed on Flag (LSON):
This bit chooses the system clock (
φ
) or subclock (
φ
SUB
) as
the CPU operating clock when watch mode is cleared. The resulting operation mode depends on
the combination of other control bits and interrupt input.
Bit 3: LSON
Description
0
The CPU operates on the system clock (
φ
) (initial
value)
1
The CPU operates on the subclock (
φ
SUB
)
Bits 2 to 0—Reserved Bits:
These bits are reserved; they are always read as 1, and cannot be
modified.
System Control Register 2 (SYSCR2)
Bit
7 6 5 4 3 2 1 0
⎯
⎯
⎯
NESEL
DTON
MSON SA1 SA0
Initial
value 1 1 1 0 0 0 0 0
Read/Write
⎯
⎯
⎯
R/W R/W R/W R/W R/W
SYSCR2 is an 8-bit read/write register for power-down mode control.
Bits 7 to 5—Reserved Bits:
These bits are reserved; they are always read as 1, and cannot be
modified.
Summary of Contents for F-ZTAT H8 Series
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