10. Serial Communication Interface
Rev.3.00 Jul. 19, 2007 page 258 of 532
REJ09B0397-0300
Receiving:
A receive operation is carried out as follows.
•
Set bits SI1 and SCK1 in PMR3 to 1 so that the respective pins function as SI
1
and SCK
1
.
•
Clear bit SNC1 in SCR1 to 0, and set bit SNC0 to 1 or 0, designating 8- or 16-bit synchronous
transfer mode. Select the serial clock in bits CKS3 to CKS0. Writing data to SCR1 initializes
the internal state of SCI1.
•
Set the SCSR1 start flag (STF) to 1. SCI1 starts operating and receives data at pin SI
1
.
•
After data reception is complete, bit IRRS1 in interrupt request register 1 (IRR1) is set to 1.
•
Read the received data from SDRL and SDRU, as follows.
⎯
8-bit transfer mode: SDRL
⎯
16-bit transfer mode: Upper byte in SDRU, lower byte in SDRL
•
After data reception is complete, an overrun occurs if the serial clock continues to be input; no
data is received and the SCSR1 overrun error flag (bit ORER) is set to 1.
Simultaneous transmit/receive:
A simultaneous transmit/receive operation is carried out as
follows.
•
Set bits SO1, SI1, and SCK1 in PMR3 to 1 so that the respective pins function as SO
1
, SI
1
, and
SCK
1
. If necessary, set bit POF1 in port mode register 2 (PMR2) for NMOS open drain output
at pin SO
1
.
•
Clear bit SNC1 in SCR1 to 0, and set bit SNC0 to 1 or 0, designating 8- or 16-bit synchronous
transfer mode. Select the serial clock in bits CKS3 to CKS0. Writing data to SCR1 initializes
the internal state of SCI1.
•
Write transmit data in SDRL and SDRU, as follows.
⎯
8-bit transfer mode: SDRL
⎯
16-bit transfer mode: Upper byte in SDRU, lower byte in SDRL
•
Set the SCSR1 start flag (STF) to 1. SCI1 starts operating. Transmit data is output at pin SO
1
.
Receive data is input at pin SI
1
.
•
After data transmission and reception are complete, bit IRRS1 in IRR1 is set to 1.
•
Read the received data from SDRL and SDRU, as follows.
⎯
8-bit transfer mode: SDRL
⎯
16-bit transfer mode: Upper byte in SDRU, lower byte in SDRL
When an internal clock is used, a serial clock is output from pin SCK
1
in synchronization with the
transmit data. After data transmission is complete, the serial clock is not output until the next time
the start flag is set to 1. During this time, pin SO
1
continues to output the value of the last bit
transmitted.
Summary of Contents for F-ZTAT H8 Series
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Page 194: ...7 RAM Rev 3 00 Jul 19 2007 page 168 of 532 REJ09B0397 0300...
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