2. CPU
Rev.3.00 Jul. 19, 2007 page 46 of 532
REJ09B0397-0300
Figure 2.6 shows the instruction code format of arithmetic, logic, and shift instructions.
15
0
8
7
op
rm
rn
ADD, SUB, CMP,
ADDX, SUBX (Rm)
Legend:
op:
rm, rn:
IMM:
Operation field
Register field
Immediate data
15
0
8
7
op
rn
ADDS, SUBS, INC, DEC,
DAA, DAS, NEG, NOT
15
0
8
7
op
rn
MULXU, DIVXU
rm
15
0
8
7
rn
IMM
ADD, ADDX, SUBX,
CMP (#XX:8)
op
15
0
8
7
op
rn
AND, OR, XOR (Rm)
rm
15
0
8
7
rn
IMM
AND, OR, XOR (#xx:8)
op
15
0
8
7
rn
SHAL, SHAR, SHLL, SHLR,
ROTL, ROTR, ROTXL, ROTXR
op
Figure 2.6 Arithmetic, Logic, and Shift Instruction Codes
Summary of Contents for F-ZTAT H8 Series
Page 6: ...Rev 3 00 Jul 19 2007 page iv of xxiv REJ09B0397 0300...
Page 194: ...7 RAM Rev 3 00 Jul 19 2007 page 168 of 532 REJ09B0397 0300...
Page 234: ...8 I O Ports Rev 3 00 Jul 19 2007 page 208 of 532 REJ09B0397 0300...
Page 274: ...9 Timers Rev 3 00 Jul 19 2007 page 248 of 532 REJ09B0397 0300...
Page 352: ...12 A D Converter Rev 3 00 Jul 19 2007 page 326 of 532 REJ09B0397 0300...
Page 561: ......
