9. Timers
Rev.3.00 Jul. 19, 2007 page 213 of 532
REJ09B0397-0300
Bit 4—Reserved Bit:
Bit 4 is reserved; it is always read as 1, and cannot be modified.
Bits 3 to 0—Internal Clock Select (TMA3 to TMA0):
Bits 3 to 0 select the clock input to TCA.
Description
Bit 3:
TMA3
Bit 2:
TMA2
Bit 1:
TMA1
Bit 0:
TMA0
Prescaler and Divider Ratio
or Overflow Period
Function
0 0 0 0 PSS,
φ
/8192 (initial
value)
Interval timer
1
PSS,
φ
/4096
1
0
PSS,
φ
/2048
1
PSS,
φ
/512
1 0 0 PSS,
φ
/256
1
PSS,
φ
/128
1
0
PSS,
φ
/32
1
PSS,
φ
/8
1 0 0 0 PSW,
1
s
Clock
time
base
1
PSW,
0.5
s
1
0
PSW,
0.25
s
1
PSW,
0.03125
s
1
0
0
PSW and TCA are reset
1
1
0
1
Timer Counter A (TCA)
Bit
7 6 5 4 3 2 1 0
TCA7 TCA6 TCA5 TCA4 TCA3 TCA2 TCA1 TCA0
Initial
value 0 0 0 0 0 0 0 0
Read/Write R R R R R R R R
TCA is an 8-bit read-only up-counter, which is incremented by internal clock input. The clock
source for input to this counter is selected by bits TMA3 to TMA0 in timer mode register A
(TMA). TCA values can be read by the CPU in active mode, but cannot be read in subactive
mode. When TCA overflows, the IRRTA bit in interrupt request register 1 (IRR1) is set to 1.
TCA is cleared by setting bits TMA3 and TMA2 of TMA to 11.
Summary of Contents for F-ZTAT H8 Series
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Page 194: ...7 RAM Rev 3 00 Jul 19 2007 page 168 of 532 REJ09B0397 0300...
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Page 352: ...12 A D Converter Rev 3 00 Jul 19 2007 page 326 of 532 REJ09B0397 0300...
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