Renesas F-ZTAT H8 Series, Hardware Manual

Page: 288 / 562

10. Serial Communication Interface
Rev.3.00 Jul. 19, 2007 page 262 of 532
REJ09B0397-0300
Pin Configuration
Table 10.4 shows the SCI3 pin configuration.
Table 10.4 Pin Configuration
Name Abbr. I/O Function
SCI3 clock SCK
3
I/O SCI3 clock input/output
SCI3 receive data input RXD Input SCI3 receive data input
SCI3 transmit data output TXD Output SCI3 transmit data output
Register Configuration
Table 10.5 shows the SCI3 internal register configuration.
Table 10.5 SCI3 Registers
Name Abbr. R/W Initial Value Address
Serial mode register SMR R/W H'00 H'FFA8
Bit rate register BRR R/W H'FF H'FFA9
Serial control register 3 SCR3 R/W H'00 H'FFAA
Transmit data register TDR R/W H'FF H'FFAB
Serial status register SSR R/W H'84 H'FFAC
Receive data register RDR R H'00 H'FFAD
Transmit shift register TSR *
⎯ ⎯
Receive shift register RSR *
⎯ ⎯
Bit rate counter BRC
*
⎯ ⎯
Legend:
⎯
: Cannot be read or written.
10.3.2 Register Descriptions
Receive Shift Register (RSR)
Bit 7 6 5 4 3 2 1 0
Read/Write
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯