Renesas F-ZTAT H8 Series Hardware Manual Download Page 176

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6. ROM

Rev.3.00 Jul. 19, 2007 page 150 of 532
REJ09B0397-0300

HD64F3857
HD64F3854

H'0000

MCU mode

Writer mode

H'EDFF

H'0000

H'EDFF

H'1FFFF

On-chip

ROM area

Undefined

values output

Figure 6.15 Memory Map in Writer Mode

Summary of Contents for F-ZTAT H8 Series

Page 1: ...ok over all the business of both companies Therefore although the old company name remains in this document it is a valid Renesas Electronics document We appreciate your understanding Renesas Electron...

Page 2: ...t for an application categorized as Specific or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics The quality grade of each Renesas...

Page 3: ...6433856 HCD6433856 H8 3855 HD6433855 HCD6433855 H8 3857 F ZTAT HD64F3857 HCD64F3857 H8 3854 HD6433854 HCD6433854 H8 3853 HD6433853 HCD6433853 H8 3852 HD6433852 HCD6433852 H8 3854 F ZTAT HD64F3854 HCD6...

Page 4: ...h quality and reliability such as safety systems or equipment or systems for transportation and traffic healthcare combustion control aerospace and aeronautics nuclear power or undersea communication...

Page 5: ...moment when power is supplied until the reset process is completed In a similar way the states of pins in a product that is reset by an on chip power on reset function are not guaranteed from the mom...

Page 6: ...Rev 3 00 Jul 19 2007 page iv of xxiv REJ09B0397 0300...

Page 7: ...functions required for system configuration a maximum 640 dot display LCD controller three types of timers a single channel serial communication interface and a 4 channel A D converter Both series ca...

Page 8: ...14 bit PWM Serial communication interface SCI 2 2 2 2 1 1 1 1 A D converter 8 ch 8 ch 8 ch 8 ch 4 ch 4 ch 4 ch 4 ch LCD controller Max display dots 1280 dots 1280 dots 1280 dots 1280 dots 640 dots 64...

Page 9: ...5 V of H8 3854F and H8 3857 Group AVCC 3 0 V to 5 5 V VSS AVSS 0 0 V Ta 20 C to 75 C unless otherwise specified including subactive mode 4 3 Subclock Generator Table 4 2 DC Characteristics and Timing...

Page 10: ...haracteristics Table15 2 DC Characteristics of H8 3855 H8 3856 and H8 3857 1 409 Table note amended Notes 4 The guaranteed temperature as an electrical characteristic for die type products is 75 C Tab...

Page 11: ...e as an electrical characteristic for die type products is 75 C 15 2 4 A D Converter Characteristics Table15 7 A D Converter Characteristics of H8 3855 H8 3856 and H8 3857 415 Table note amended Notes...

Page 12: ...ded 5 0 2 5 0 5 1 0 VCC V Active mode high speed Sleep mode except CPU MHz 5 5 625 0 500 0 312 5 62 5 3 0 2 7 VCC V Active mode medium speed kHz 4 0 5 5 16 384 19 200 8 192 9 600 4 096 4 800 VCC V Sub...

Page 13: ...rature as an electrical characteristic for die type products is 75 C Table 16 3 DC Characteristics of H8 3852 H8 3853 and H8 3854 2 430 Table condition amended VCC 2 7 V to 5 5 V of the mask ROM versi...

Page 14: ...H8 3854 VCC 3 0 V to 5 5 V of H8 3854F VSS 0 0 V Ta 20 C to 75 C unless otherwise specified Table note amended Note The guaranteed temperature as an electrical characteristic for die type products is...

Page 15: ...f xxiv REJ09B0397 0300 Item Page Revision See Manual for Details B 2 Register Descriptions PMR2 Port mode register 2 492 Bit table amended P4 IRQ pin function switch 1 0 Functions as P4 input pin 1 Fu...

Page 16: ...Rev 3 00 Jul 19 2007 Page xiv of xxiv REJ09B0397 0300 All trademarks and registered trademarks are the property of their respective owners...

Page 17: ...Formats 31 2 3 1 Data Formats in General Registers 32 2 3 2 Memory Data Formats 33 2 4 Addressing Modes 34 2 4 1 Addressing Modes 34 2 4 2 Effective Address Calculation 36 2 5 Instruction Set 40 2 5...

Page 18: ...nterrupts 73 3 3 1 Overview 73 3 3 2 Interrupt Control Registers 75 3 3 3 External Interrupts 83 3 3 4 Internal Interrupts 84 3 3 5 Interrupt Operations 84 3 3 6 Interrupt Response Time 89 3 4 Applica...

Page 19: ...ve Mode 113 5 6 1 Transition to Subactive Mode 113 5 6 2 Clearing Subactive Mode 113 5 6 3 Operating Frequency in Subactive Mode 114 5 7 Active medium speed Mode 114 5 7 1 Transition to Active medium...

Page 20: ...ing Flash Memory Programming and Erasing 148 6 8 Flash Memory Writer Mode 149 6 8 1 Writer Mode Setting 149 6 8 2 Socket Adapter and Memory Map 149 6 8 3 Writer Mode Operation 153 6 8 4 Memory Read Mo...

Page 21: ...onfiguration and Description 194 8 5 3 Pin Functions 196 8 5 4 Pin States 197 8 6 Port 5 197 8 6 1 Overview 197 8 6 2 Register Configuration and Description 198 8 6 3 Pin Functions 200 8 6 4 Pin State...

Page 22: ...mer F 226 9 5 1 Overview 226 9 5 2 Register Descriptions 229 9 5 3 Interface with the CPU 235 9 5 4 Timer Operation 238 9 5 5 Application Notes 240 9 6 Watchdog Timer H8 3857F and H8 3854F Only 241 9...

Page 23: ...tion 314 Section 12 A D Converter 315 12 1 Overview 315 12 1 1 Features 315 12 1 2 Block Diagram 316 12 1 3 Pin Configuration 317 12 1 4 Register Configuration 317 12 2 Register Descriptions 318 12 2...

Page 24: ...Display 347 13 3 5 Display Data Output 349 13 3 6 Register and Display Memory Access 353 13 3 7 Scroll Function 356 13 3 8 Blink Function 358 13 3 9 Module Standby Mode 360 13 3 10 Power On and Power...

Page 25: ...rd Specifications 403 15 2 H8 3855 H8 3856 and H8 3857 Electrical Characteristics Standard Specifications 404 15 2 1 Power Supply Voltage and Operating Range 404 15 2 2 DC Characteristics 406 15 2 3 A...

Page 26: ...459 B 1 2 H8 3854 Group Addresses 464 B 2 Register Descriptions 468 Appendix C I O Port Block Diagrams 508 C 1 Block Diagram of Port 1 508 C 2 Block Diagram of Port 2 513 C 3 Block Diagram of Port 3...

Page 27: ...ally suited for embedded control of systems requiring an LCD display The H8 3857 Group comprises the H8 3855 with 40 kbytes of ROM and 2 kbytes of RAM on chip the H8 3856 with 48 kbytes of ROM and 2 k...

Page 28: ...s MOV instruction for data transfer between memory and registers Typical instructions Multiply 8 bits 8 bits Divide 16 bits 8 bits Bit accumulator Register indirect designation of bit position Interru...

Page 29: ...29 I O port pins I O pins 24 Input pins 5 Timers Four on chip timers three in the H8 3854 Group Timer A 8 bit timer Count up timer with selection of eight internal clock signals divided from the syste...

Page 30: ...solution 8 bits 8 channel analog input port Conversion time 31 or 62 per channel H8 3854 Group Successive approximations using a resistance ladder resolution 8 bits 4 channel analog input port Convers...

Page 31: ...HD64F3857TG 144 pin TQFP TFP 144 RAM 2 kbytes HCD6433857 HCD64F3857 Die H8 3854 Group Part No Mask ROM Version 2 F ZTAT Version Package ROM RAM Size HD6433852H 100 pin QFP FP 100B ROM 16 kbytes HD643...

Page 32: ...TMIB P16 IRQ2 TMIC P17 IRQ3 TMIF P20 IRQ4 ADTRG P21 UD P22 P23 P24 P25 P26 P27 P30 SCK1 P31 SI1 P32 SO1 P33 P34 P35 P36 P37 V5OUT V4OUT V3OUT V2OUT V1OUT V4 V34 V3 VLCD P40 SCK3 P41 RXD P42 TXD P43 IR...

Page 33: ...0 IRQ4 ADTRG P21 P22 P23 P24 P25 P26 P27 V1OUT V2OUT V3OUT V4OUT V5OUT P40 SCK3 P41 RXD P42 TXD P43 IRQ0 FLASH MASK ROM Timer A Timer B Timer F SCI3 A D Internal I O port RAM P57 WKP7 P56 WKP6 P55 WKP...

Page 34: ...100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 COM17 SEG56 COM18 SEG55 COM19 SEG54 COM20 SEG53 COM21 SEG52 COM22 SEG51 COM23 SEG50 COM24 SEG49 COM25 SEG48 COM26 S...

Page 35: ...18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93...

Page 36: ...11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 143 144 141 142 139 140 137 138 135 136 133 134 131 132 129 130 127 125 128 126 123 124 121 122 119 120 117 118 115 116 11...

Page 37: ...46 COM10 SEG63 1394 3463 81 SEG29 3348 1627 12 P24 3348 771 47 COM11 SEG62 1231 3463 82 SEG30 3348 1467 13 P23 3348 637 48 COM12 SEG61 1069 3463 83 SEG31 3348 1307 14 P22 3348 503 49 COM13 SEG60 905 3...

Page 38: ...13 1761 3463 108 COM17 SEG56 3348 2863 123 VLCD 395 3463 138 P12 TMOFH 1911 3463 109 V5OUT 2776 3463 124 VSS 226 3463 139 P11 TMOFL 2045 3463 110 V4OUT 2616 3463 125 P37 74 3463 140 P10 TMOW 2180 3463...

Page 39: ...36 143 144 141 142 139 140 137 138 135 136 133 134 131 132 129 130 127 125 128 126 123 124 121 122 119 120 117 118 115 116 113 114 111 112 109 110 38 37 40 39 42 41 44 43 46 45 48 47 50 49 52 51 54 5...

Page 40: ...15 P21 UD 2913 621 50 COM14 SEG59 585 2913 85 SEG33 2913 715 16 P20 IRQ4 ADTRG 2913 491 51 COM15 SEG58 455 2913 86 SEG34 2913 585 17 AVCC 2913 290 52 COM16 SEG57 325 2913 87 SEG35 2913 455 18 PB0 AN0...

Page 41: ...2913 111 V3OUT 2125 2913 124 VSS 325 2913 137 P13 1365 2913 112 V2OUT 1975 2913 125 P37 195 2913 138 P12 TMOFH 1505 2913 113 V1OUT 1825 2913 126 P36 65 2913 139 P11 TMOFL 1645 2913 114 V4 1675 2913 1...

Page 42: ...0 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90...

Page 43: ...2 SEG37 1226 2985 15 P20 IRQ4 ADTRG 2985 396 48 SEG3 2055 2985 83 SEG38 1025 2985 16 TEST2 2985 558 49 SEG4 2259 2985 84 SEG39 823 2985 17 X2 2985 716 50 SEG5 2463 2985 85 SEG40 621 2985 18 X1 2985 87...

Page 44: ...25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 Model Y X 0 0 Model HD643385rccc r Number deno...

Page 45: ...161 16 TEST2 2161 259 50 SEG5 1721 2161 83 SEG38 760 2161 17 X2 2161 389 51 SEG6 2161 1721 84 SEG39 630 2161 18 X1 2161 519 52 SEG7 2161 1551 85 SEG40 500 2161 19 VSS 2161 764 53 SEG8 2161 1383 86 V5O...

Page 46: ...C 17 17 Input Analog power supply H8 3857 Group only This is the power supply pin for the A D converter When the A D converter is not used connect this pin to the system power supply 5 V AVSS 26 26 In...

Page 47: ...e VSS potential Interrupt pins IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 141 135 134 133 16 141 135 134 133 16 96 92 91 15 96 92 91 15 Input External interrupt request 4 to 0 H8 3857 Group External interrupt request 4...

Page 48: ...by the timer FH output compare function 14 bit PWM pin PWM 136 136 Output 14 bit PWM output H8 3857 Group only This is an output pin for waveforms generated by the 14 bit PWM I O ports PB7 to PB4 PB3...

Page 49: ...ated for each bit by means of port control register 5 PCR5 Internal I O ports PA3 to PA0 I O Port A This is a 4 bit I O port Input or output can be designated for each bit by means of port control reg...

Page 50: ...LCD controller COM32 to COM17 COM16 to COM1 93 to 108 52 to 37 93 to 108 52 to 37 45 to 30 45 to 30 Output LCD common output These are LCD common output pins The maximum number of pins is 32 in the H8...

Page 51: ...e built in op amp drive capacity is inadequate connect a capacitor to provide stabilization If levels V1 to V5 are input from an external source set the OPON bit low Vci 117 117 Input LCD step up circ...

Page 52: ...V5OUT 90 to 86 90 to 86 I O LCD drive power supply level H8 3854 Group When the LPS1 and LPS0 bits are set high these pins output LCD drive power supply levels V1 to V5 If the drive capacity is inade...

Page 53: ...ctions including Multiply and divide instructions Powerful bit manipulation instructions Eight addressing modes Register direct Register indirect Register indirect with displacement Register indirect...

Page 54: ...s the register structure of the H8 300L CPU There are two groups of registers the general registers and control registers 7 0 7 0 15 0 PC R0H R1H R2H R3H R4H R5H R6H R7H R0L R1L R2L R3L R4L R5L R6L R7...

Page 55: ...the stack pointer as indicated in figure 2 2 SP R7 points to the top of the stack Lower address side H 0000 Upper address side H FFFF Unused area Stack area SP R7 Figure 2 2 Stack Pointer 2 2 2 Contro...

Page 56: ...ADD W SUB W or CMP W instruction is executed the H flag is set to 1 if there is a carry or borrow at bit 11 and is cleared to 0 otherwise Bit 4 User Bit U Can be used freely by the user Bit 3 Negativ...

Page 57: ...zed by software by the first instruction executed after a reset 2 3 Data Formats The H8 300L CPU can process 1 bit data 4 bit BCD data 8 bit byte data and 16 bit word data Bit manipulation instruction...

Page 58: ...nH 7 6 5 4 3 2 1 0 don t care 7 0 1 bit data RnL MSB LSB don t care 7 0 Byte data RnH Byte data RnL Word data Rn 4 bit BCD data RnH 4 bit BCD data RnL Legend RnH RnL MSB LSB Upper byte of general regi...

Page 59: ...plies to instruction fetching Data Format 7 6 5 4 3 2 1 0 Address Data Type 7 0 Address n MSB LSB MSB LSB Upper 8 bits Lower 8 bits MSB LSB CCR CCR MSB LSB MSB LSB Address n Even address Odd address E...

Page 60: ...mory indirect aa 8 1 Register Direct Rn The register field of the instruction specifies an 8 or 16 bit general register containing the operand Only the MOV W ADD W SUB W CMP W ADDS SUBS MULXU 8 bits 8...

Page 61: ...es the absolute address of the operand in memory The absolute address may be 8 bits long aa 8 or 16 bits long aa 16 The MOV B and bit manipulation instructions can use 8 bit absolute addresses The MOV...

Page 62: ...nificant bit is regarded as 0 causing word access to be performed at the address preceding the specified address See section 2 3 2 Memory Data Formats for further information 2 4 2 Effective Address C...

Page 63: ...Register indirect Rn Contents 16 bits of register indicated by rm 0 15 0 15 3 Register indirect with displacement d 16 Rn op rm 7 6 3 4 0 15 disp 0 15 disp 0 15 Contents 16 bits of register indicated...

Page 64: ...e Address Calculation Method Effective Address EA 5 Absolute address aa 8 aa 16 op 8 7 0 15 0 15 abs H FF 8 7 0 15 0 15 abs op 6 op 0 15 IMM xx 16 op 8 7 0 15 IMM Immediate xx 8 Operand is 1 or 2 byte...

Page 65: ...de and Instruction Format Effective Address Calculation Method Effective Address EA 8 Memory indirect aa 8 op 8 7 0 15 Memory contents 16 bits 0 15 abs H 00 8 7 0 15 abs Legend rm rn Register field op...

Page 66: ...T 4 Shift SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR 8 Bit manipulation BSET BCLR BNOT BTST BAND BIAND BOR BIOR BXOR BIXOR BLD BILD BST BIST 14 Branch Bcc 2 JMP BSR JSR RTS 5 System control RTE SLEEP L...

Page 67: ...dition code register N N negative flag of CCR Z Z zero flag of CCR V V overflow flag of CCR C C carry flag of CCR PC Program counter SP Stack pointer IMM Immediate data disp Displacement Addition Subt...

Page 68: ...data to a general register The Rn Rn d 16 Rn aa 16 xx 16 Rn and Rn addressing modes are available for byte or word data The aa 8 addressing mode is available for byte data only The R7 and R7 modes req...

Page 69: ...isp 15 0 8 7 op rm rn Rm Rn or Rn Rm 15 0 8 7 op rn abs aa 8 Rn 15 0 8 7 op rn aa 16 Rn abs 15 0 8 7 op rn IMM xx 8 Rn 15 0 8 7 op rn xx 16 Rn IMM 15 0 8 7 op rn PUSH POP Legend op rm rn disp abs IMM...

Page 70: ...s or decrements a general register by 1 ADDS SUBS W Rd 1 Rd Rd 2 Rd Adds or subtracts immediate data to or from data in a general register The immediate data must be 1 or 2 DAA DAS B Rd decimal adjust...

Page 71: ...s a logical exclusive OR operation on a general register and another general register or immediate data NOT B Rd Rd Obtains the one s complement logical complement of general register contents Note Si...

Page 72: ...DX SUBX Rm Legend op rm rn IMM Operation field Register field Immediate data 15 0 8 7 op rn ADDS SUBS INC DEC DAA DAS NEG NOT 15 0 8 7 op rn MULXU DIVXU rm 15 0 8 7 rn IMM ADD ADDX SUBX CMP XX 8 op 15...

Page 73: ...lower three bits of a general register BTST B bit No of EAd Z Tests a specified bit in a general register or memory operand and sets or clears the Z flag accordingly The bit number is specified by 3...

Page 74: ...Copies a specified bit in a general register or memory operand to the C flag BILD B bit No of EAd C Copies the inverse of a specified bit in a general register or memory operand to the C flag The bit...

Page 75: ...n 0 0 0 0 0 0 0 IMM 15 0 8 7 op 0 Operand Bit No register indirect Rn register direct Rm rn 0 0 0 0 0 0 0 rm op 15 0 8 7 op Operand Bit No absolute aa 8 immediate xx 3 abs 0 0 0 0 IMM op op 15 0 8 7 o...

Page 76: ...ess Immediate data 15 0 8 7 op IMM rn Operand Bit No register direct Rn immediate xx 3 BIAND BIOR BIXOR BILD BIST 15 0 8 7 op 0 Operand Bit No register indirect Rn immediate xx 3 rn 0 0 0 0 0 0 0 IMM...

Page 77: ...Description Condition BRA BT Always true Always BRN BF Never false Never BHI High C Z 0 BLS Low or same C Z 1 BCC BHS Carry clear high or same C 0 BCS BLO Carry set low C 1 BNE Not equal Z 0 BEQ Equal...

Page 78: ...eld Register field Displacement Absolute address 15 0 8 7 op cc disp Bcc 15 0 8 7 op rm 0 JMP Rm 0 0 0 15 0 8 7 op JMP aa 16 abs 15 0 8 7 op abs JMP aa 8 15 0 8 7 op disp BSR 15 0 8 7 op rm 0 JSR Rm 0...

Page 79: ...ode See section 5 Power Down Modes for details LDC B Rs CCR IMM CCR Moves immediate data or general register contents to the condition code register STC B CCR Rd Copies the condition code register to...

Page 80: ...gure 2 10 shows its object code format Table 2 11 Block Data Transfer Instruction Instruction Size Function EEPMOV if R4L 0 then repeat R5 R6 R4L 1 R4L until R4L 0 else next Block transfer instruction...

Page 81: ...state A bus cycle consists of two states or three states The cycle differs depending on whether access is to on chip memory or to on chip peripheral modules 2 6 1 Access to On Chip Memory RAM ROM Acce...

Page 82: ...means that for accessing word data two instructions must be used Figures 2 12 and 2 13 show the on chip peripheral module access cycle Two State Access to On Chip Peripheral Modules T1 state Bus cycle...

Page 83: ...te data SUB or Figure 2 13 On Chip Peripheral Module Access Cycle 3 State Access 2 7 CPU States 2 7 1 Overview There are four CPU states the reset state program execution state program halt state and...

Page 84: ...y the system clock The CPU executes successive program instructions at reduced speed synchronized by the system clock The CPU executes successive program instructions at reduced speed synchronized by...

Page 85: ...is synchronized with the system clock in active mode high speed and medium speed and with the subclock in subactive mode See section 5 Power Down Modes for details on these modes 2 7 3 Program Halt S...

Page 86: ...54 Group are shown in figures 2 16 a and b H 0000 H 0029 H 002A H 9FFF H BFFF H EDFF H FF7F H FF80 H FFFF Interrupt vector 42 bytes On chip ROM 40 kbytes 2 048 bytes On chip RAM Internal I O registers...

Page 87: ...Not used H 3FFF H 5FFF H 7FFF H F77F H F780 H FF7F H FF80 H8 3852 H8 3853 H8 3854 24 kbytes 32 kbytes 60 kbytes H8 3852 H8 3853 H8 3854 1 H8 3854F 1 2 048 bytes 2 H8 3854F Notes 1 Note that the H8 38...

Page 88: ...to Internal I O Registers Internal data transfer to or from on chip modules other than the ROM and RAM areas makes use of an 8 bit data width If word access is attempted to these areas the following...

Page 89: ...and H8 3854F 1 The H8 3855 has 40 kbytes of on chip ROM ending at address H 9FFF the H8 3856 has 48 kbytes ending at address H BFFF the H8 3852 has 16 kbytes ending at address H 3FFF the H8 3853 has...

Page 90: ...ter and timer count bit manipulation Figure 2 18 shows an example in which two timer registers share the same address When a bit manipulation instruction accesses the timer load register and timer cou...

Page 91: ...0 B BSET instruction executed BSET 0 PDR3 The BSET instruction is executed designating port 3 C After executing BSET P37 P36 P35 P34 P33 P32 P31 P30 Input output Input Input Output Output Output Outp...

Page 92: ...R3 P37 P36 P35 P34 P33 P32 P31 P30 Input output Input Input Output Output Output Output Output Output Pin state Low level High level Low level Low level Low level Low level Low level Low level PCR3 0...

Page 93: ...utput Pin state Low level High level Low level Low level Low level Low level Low level Low level PCR3 0 0 1 1 1 1 1 1 PDR3 1 0 0 0 0 0 0 0 B BCLR instruction executed BCLR 0 PCR3 The BCLR instruction...

Page 94: ...s well as to PCR3 P37 P36 P35 P34 P33 P32 P31 P30 Input output Input Input Output Output Output Output Output Output Pin state Low level High level Low level Low level Low level Low level Low level Lo...

Page 95: ...A 1 PDRA H FFDD Notes 1 These port registers are used also for pin input 2 A function of the H8 3857 Group only not provided in the H8 3854 Group 3 Some bits are not present in the H8 3854 Group Tabl...

Page 96: ...on It moves the number of bytes specified by R4L from the address specified by R5 to the address specified by R6 R5 R5 R4L R6 R6 R4L When setting R4L and R6 make sure that the final destination addres...

Page 97: ...rs of the on chip peripheral modules are initialized 3 2 2 Reset Sequence As soon as the RES pin goes low all processing is stopped and the H8 3857 enters the reset state To make sure the chip is rese...

Page 98: ...irst instruction of program 2 3 2 Reset cleared 1 Figure 3 1 Reset Sequence 3 2 3 Interrupt Immediately after Reset After a reset if an interrupt were to be accepted before the stack pointer SP R7 was...

Page 99: ...P7 to WKP0 IRQ4 IRQ3 IRQ1 and IRQ0 and 14 internal interrupts from on chip peripheral modules Table 3 2 shows the interrupt sources their priorities and their vector addresses When more than one inter...

Page 100: ...A overflow 11 H 0016 to H 0017 Timer B Timer B overflow 12 H 0018 to H 0019 Timer C 2 Timer C overflow or underflow 13 H 001A to H 001B Timer FL Timer FL compare match 14 H 001C to H 001D Timer FL ov...

Page 101: ...flag 2 There are some differences in functions between the H8 3857 Group and the H8 3854 Group For details see the individual register descriptions IRQ Edge Select Register IEGR Bit 7 6 5 4 3 2 1 0 IE...

Page 102: ...nput is detected Bit 1 IRQ1 Edge Select IEG1 Bit 1 selects the input sensing of pin IRQ1 TMIB Bit 1 IEG1 Description 0 Falling edge of IRQ1 TMIB pin input is detected initial value 1 Rising edge of IR...

Page 103: ...Interrupt Enable IENWP Bit 5 enables or disables WKP7 to WKP0 interrupt requests Bit 5 IENWP Description 0 Disables interrupt requests from WKP7 to WKP0 initial value 1 Enables interrupt requests fro...

Page 104: ...ransfer interrupt requests Bit 7 IENDT Description 0 Disables direct transfer interrupt requests initial value 1 Enables direct transfer interrupt requests Bit 6 A D Converter Interrupt Enable IENAD B...

Page 105: ...s or disables timer B overflow or underflow interrupt requests Bit 0 IENTB Description 0 Disables timer B interrupts initial value 1 Enables timer B interrupts SCI3 interrupt control is covered in 10...

Page 106: ...ompleted Bit 5 Reserved Bit Bit 5 is reserved it is always read as 1 and cannot be modified Bits 4 3 1 and 0 IRQ4 IRQ3 IRQ1 and IRQ0 Interrupt Request Flags IRRI4 IRRI3 IRRI1 IRRI0 Bit n IRRIn Descrip...

Page 107: ...imer C or timer B interrupt is requested The flags are not cleared automatically when an interrupt is accepted It is necessary to write 0 to clear each flag Bit 7 Direct Transfer Interrupt Request Fla...

Page 108: ...1 it is cleared by writing 0 initial value 1 Setting condition When counter FL matches output compare register FL in 8 bit timer mode Bit 1 Timer C Interrupt Request Flag IRRTC Bit 1 is used in the H8...

Page 109: ...ling edge input is detected at the pin Note n 7 to 0 3 3 3 External Interrupts The H8 3857 Group has 13 external interrupt sources WKP7 to WKP0 and IRQ4 to IRQ0 The H8 3854 Group has 12 external inter...

Page 110: ...When a peripheral module requests an interrupt the corresponding bit in IRR1 or IRR2 is set to 1 Individual interrupt requests can be disabled by clearing the corresponding bit in IENR1 or IENR2 to 0...

Page 111: ...ndling routine located at the address indicated by the contents of the vector address is executed Notes 1 When disabling interrupts by clearing bits in an interrupt enable register or when clearing bi...

Page 112: ...IENDT 1 No Yes IRRDT 1 No Yes Branch to interrupt handling routine IRRI0 1 No Yes IEN1 1 No Yes IRRI1 1 No Yes IEN2 1 No Yes IRRI2 1 Legend PC Program counter CCR Condition code register I I bit of C...

Page 113: ...its of program counter PC Condition code register Stack pointer Ignored on return from interrupt Notes CCR CCR PCH PCL PC shows the address of the first instruction to be executed upon return from the...

Page 114: ...tion is not executed Address is saved as PC contents becoming return address 2 4 Instruction code not executed 3 Instruction prefetch address Instruction is not executed 5 SP 2 6 SP 4 7 CCR 8 Vector a...

Page 115: ...CCR to stack 4 Vector fetch 2 Instruction fetch 4 Internal processing 4 Total 15 to 27 Note Not including EEPMOV instruction 3 4 Application Notes 3 4 1 Notes on Stack Area Use When word data is acces...

Page 116: ...on return the even address contents are restored to CCR while the odd address contents are ignored 3 4 2 Notes on Rewriting Port Mode Registers When a port mode register is rewritten to switch the fun...

Page 117: ...while pin IRQ1 is low and IEGR bit IEG1 0 When PMR1 bit IRQ1 is changed from 1 to 0 while pin IRQ1 is low and IEGR bit IEG1 1 IRRI0 When PMR2 bit IRQ0 is changed from 0 to 1 while pin IRQ0 is low and...

Page 118: ...out executing an intervening instruction the flag will not be cleared An alternative method is to avoid the setting of interrupt request flags when pin functions are switched by keeping the pins at th...

Page 119: ...ram Figure 4 1 shows a block diagram of the clock pulse generators System clock oscillator System clock divider 1 2 Subclock oscillator Subclock divider 1 2 1 4 1 8 System clock divider 1 8 System clo...

Page 120: ...ystal or ceramic oscillator or by providing external clock input Connecting a Crystal Oscillator Figure 4 2 shows a typical method of connecting a crystal oscillator 1 2 C1 C2 OSC OSC R 1 M 20 C C 12...

Page 121: ...or Notes on Board Design When generating clock pulses by connecting a crystal or ceramic oscillator pay careful attention to the following points Avoid running signal lines close to the oscillator cir...

Page 122: ...R 500 30 Figure 4 6 Example of Connection when Inputting an External Clock Frequency OSC clock osc Duty 45 to 55 4 3 Subclock Generator Connecting a 32 768 kHz Crystal Oscillator Clock pulses can be...

Page 123: ...ternal Clock Circuit configuration An external clock is input to the X1 pin The X2 pin should be left open An example of the connection in this case is shown in figure 4 9 X X 1 2 Open External clock...

Page 124: ...including subactive mode Item Symbol Applicable Pin Test Conditions Values Min Typ Max Unit Notes Input high voltage VIH X1 VCC 0 3 VCC 0 3 V Figure 4 10 Input low voltage VIL 0 3 0 3 External subclo...

Page 125: ...ock pulse generator stops Prescaler S also stops and is initialized to H 0000 The CPU cannot read or write prescaler S The output from prescaler S is shared by timer A timer B timer C timer F SCI1 SCI...

Page 126: ...refully evaluated by the user referring to the examples shown in this section Oscillator circuit constants will differ depending on the oscillator element stray capacitance in its interconnecting circ...

Page 127: ...ecuting program instructions at reduced speed Sleep mode The CPU halts On chip peripheral modules continue to operate on the system clock Subsleep mode The CPU halts Timer A timer C and the LCD contro...

Page 128: ...2 A transition between different modes cannot be made to occur simply because an interrupt request is generated Make sure that the interrupt is accepted and interrupt handling is performed Details on...

Page 129: ...s 3 Functions 3 Functions 3 Retained Timer B Retained Retained Retained Peripheral module functions Timer C 6 Functions Retained 2 Functions Retained 2 Timer F Retained Retained SCI1 6 Functions Funct...

Page 130: ...SON Initial value 0 0 0 0 0 1 1 1 Read Write R W R W R W R W R W SYSCR1 is an 8 bit read write register for control of the power down modes Bit 7 Software Standby SSBY This bit designates transition t...

Page 131: ...e 131 072 states Legend Don t care Bit 3 Low Speed on Flag LSON This bit chooses the system clock or subclock SUB as the CPU operating clock when watch mode is cleared The resulting operation mode dep...

Page 132: ...ctive mode a transition is made to standby mode watch mode or sleep mode initial value When a SLEEP instruction is executed in subactive mode a transition is made to watch mode or subsleep mode 1 When...

Page 133: ...ote This is a function of the H8 3857 Group only and is not provided in the H8 3854 Group 5 2 2 Clearing Sleep Mode Sleep mode is cleared by an interrupt timer A timer B timer C timer F IRQ0 IRQ1 IRQ2...

Page 134: ...ck pulse generator starts After the time set in bits STS2 STS0 in SYSCR1 has elapsed a stable system clock signal is supplied to the entire chip standby mode is cleared and interrupt exception handlin...

Page 135: ...0 0 should be set 5 3 4 Transition to Standby Mode and Port Pin States The system goes from active high speed or medium speed mode to standby mode when a SLEEP instruction is executed while the SSBY b...

Page 136: ...n external input signals cannot be captured because internal clock stops The case of falling edge capture is illustrated in figure 5 3 As shown in the case marked Capture not possible when an external...

Page 137: ...nput pins to which these notes apply IRQ4 IRQ3 IRQ2 IRQ1 IRQ0 WKP7 to WKP0 ADTRG TMIB TMIC TMIF Note H8 3857 Group pin not provided in the H8 3854 Group 5 4 Watch Mode 5 4 1 Transition to Watch Mode T...

Page 138: ...RES pin is the same as for standby mode see section 5 3 2 Clearing Standby Mode 5 4 3 Oscillator Settling Time after Watch Mode Is Cleared The waiting time is the same as for standby mode see section...

Page 139: ...the LSON bit in SYSCR1 is set to 1 From subsleep mode subactive mode is entered if a timer A timer C IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 or WKP0 to WKP7 interrupt is requested A transition to subactive mode doe...

Page 140: ...ve medium speed Mode Active medium speed mode is cleared by a SLEEP instruction or by a input at the RES pin Clearing by SLEEP Instruction A transition to standby mode takes place if a SLEEP instructi...

Page 141: ...ep mode Direct Transfer from Active Medium Speed Mode to Active High Speed Mode When a SLEEP instruction is executed in active medium speed mode while the SSBY and LSON bits in SYSCR1 are cleared to 0...

Page 142: ...cution to interrupt exception handling completion is calculated by expression 1 below Direct transfer time number of states for SLEEP instruction execution number of states for internal processing tcy...

Page 143: ...number of states for interrupt exception handling execution tcyc after transition 3 Example Direct transfer time for the H8 3857 Group and H8 3854 Group when CPU clock frequency is w 8 and wait time i...

Page 144: ...on is performed via watch mode see section 5 3 5 Notes on External Input Signal Changes before after Standby Mode 2 Direct transition from active medium speed mode to subactive mode Since the mode tra...

Page 145: ...eed 2 state data access for both byte data and word data With the flash memory versions H8 3857F H8 3854F programs can be written and erased and programmed either with a general purpose PROM programme...

Page 146: ...memory can be reprogrammed up to 100 times On board programming modes There are two modes in which flash memory can be programmed erased verified on board Boot mode User program mode Automatic bit ra...

Page 147: ...R MDCR H 0000 H 0002 H 0004 H EDFC H EDFE Upper byte even address Lower byte odd address H 0001 H 0003 H 0005 H EDFD H EDFF On chip flash memory 60 kbytes The registers that control the flash memory F...

Page 148: ...programmed or erased Modes in which the flash memory can be programmed and erased are boot mode user program mode and Writer mode Boot mode On board programming mode User program mode User mode Reset...

Page 149: ...hipped The procedure for rewriting an old version of an application program or data is described here The user should prepare a programming control program and the new application program beforehand i...

Page 150: ...E pin and the program that will transfer the programming erase control program from flash memory to on chip RAM should be written into the flash memory by the user beforehand The programming erase con...

Page 151: ...ock one 16 kbyte block one 28 kbyte block and four 1 kbyte blocks Address H 0000 Address H EDFF 60 kbytes 28 kbytes 1 kbyte 1 kbyte 1 kbyte 1 kbyte 16 kbytes 12 kbytes Figure 6 6 Flash Memory Blocks 6...

Page 152: ...pin or if a high level is input and the SWE bit in FLMCR1 is not set these registers are initialized to H 00 5 FLMCR1 FLMCR2 and EBR are 8 bit registers Only byte accesses are valid for these registe...

Page 153: ...ation on the use of this bit Bit 7 FWE Description 0 When a low level is input to the FWE pin hardware protected state 1 When a high level is input to the FWE pin Bit 6 Software Write Enable SWE 1 2 B...

Page 154: ...0 selects program mode transition or clearing Do not set the SWE ESU PSU EV PV or E bit at the same time Bit 0 P Description 0 Program mode cleared initial value 1 Transition to program mode Setting...

Page 155: ...asing When FLER is set to 1 flash memory goes to the error protection state Bit 7 FLER Description 0 Flash memory is operating normally Flash memory program erase protection error protection is disabl...

Page 156: ...e 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W EBR is a register that specifies the flash memory erase area block by block Bits 6 to 0 of EBR are read write bits EBR is initialized to H 00 b...

Page 157: ...R is an 8 bit read only register used to monitor the current operating mode of the H8 3857F Bits 7 to 2 Reserved Bits Bits 7 to 2 are reserved they are always read as 0 and cannot be modified Bits 1 a...

Page 158: ...rol registers are selected for addresses H FF80 to H FF83 Bits 2 to 0 Reserved Bits Bits 2 to 0 are reserved they are always read as 0 and cannot be modified 6 4 On Board Programming Modes When an on...

Page 159: ...3 to the programming control program area in the on chip RAM After the transfer is completed execution branches to the start address H FB80 of the programming control program area and the programming...

Page 160: ...0 and transmits one H 55 data byte After bit rate adjustment chip transmits one H 00 data byte to host to indicate end of adjustment Host transmits number of programming control program bytes N upper...

Page 161: ...reset and repeat the above operations Depending on the host s transmission bit rate and the chip s system clock frequency there will be a discrepancy between the bit rates of the host and the chip To...

Page 162: ...is reserved as an area for use by the boot program as shown in figure 6 10 The area to which the programming control program is transferred comprises addresses H FB80 to H FF7F The boot program area b...

Page 163: ...o these registers must be initialized immediately after branching to the programming control program In particular since the stack pointer SP is used implicitly in subroutine calls etc a stack area mu...

Page 164: ...carried out by providing on board means of FWE control and supply of programming data and incorporating a programming erase control program in part of the program area as necessary To select user prog...

Page 165: ...EST2 1 TEST 0 Reset start Write FWE assessment program and transfer program and programming erase control program if necessary beforehand Do not apply a constant high level to the FWE pin A high level...

Page 166: ...Programming should be performed in the erased state Do not perform additional programming on addresses that have already been programmed 6 5 1 Program Mode When writing data or programs to flash memor...

Page 167: ...2 is cleared at least s later The watchdog timer is cleared following the elapse of more than y z s after being set and the operating mode is switched to program verify mode by setting the PV bit in F...

Page 168: ...all 32 bytes have been erased Data transfer is performed by byte transfer word transfer is not possible The lower 8 bits of the first address written to must be H 00 H 20 H 40 H 60 H 80 H A0 H C0 or H...

Page 169: ...ting the erase procedure 6 5 4 Erase Verify Mode In erase verify mode data is read after memory has been erased to check whether it has been correctly erased After the elapse of the erase time erase m...

Page 170: ...s Clear EV bit in FLMCR1 Clear SWE bit in FLMCR1 Disable WDT Erase halted 1 Verify data all 1 Last address of block End of erasing of all erase blocks Erase failure Clear SWE bit in FLMCR1 n N No No...

Page 171: ...he program erase protected state is entered 3 Not possible Not possible 2 Not possible Reset standby protection In a reset including a WDT overflow reset and in standby mode FLMCR1 FLMCR2 and EBR are...

Page 172: ...When not erasing clear all EBR bits to 0 6 6 3 Error Protection In error protection an error is detected when MCU runaway occurs during flash memory programming erasing 1 or operation is not performe...

Page 173: ...not possible Verify read not possible Programming not possible Erasing not possible Register FLMCR1 FLMCR2 EBR initialization state RD VF PR ER INIT RD VF PR ER FLER 0 Error occurrence Error occurren...

Page 174: ...1 Interrupt occurrence during programming or erasing might cause a violation of the programming or erasing algorithm with the result that normal operation could not be assured 2 In the interrupt exce...

Page 175: ...and in status read mode detailed internal signals are output after execution of an auto program or auto erase operation 6 8 2 Socket Adapter and Memory Map In Writer mode a socket adapter for the rel...

Page 176: ...ev 3 00 Jul 19 2007 page 150 of 532 REJ09B0397 0300 HD64F3857 HD64F3854 H 0000 MCU mode Writer mode H EDFF H 0000 H EDFF H 1FFFF On chip ROM area Undefined values output Figure 6 15 Memory Map in Writ...

Page 177: ...4 PB5 PB6 Vci VLCD VSS AVSS TEST2 PB4 RES OSC1 OSC2 NC OPEN HD64F3857 Socket Adapter 32 Pin Conversion Legend FWE FO7 to FO0 FA15 to FA0 OE CE WE Flash write enable Data input output Address input Out...

Page 178: ...PB6 VSS TEST2 PB4 RES OSC1 OSC2 HD64F3854 Socket Adapter 32 Pin Conversion Pin Name FWE FO0 FO1 FO2 FO3 FO4 FO5 FO6 FO7 FA0 FA1 FA2 FA3 FA4 FA5 FA6 FA7 FA8 FA9 FA10 FA11 FA12 FA13 FA14 FA15 CE OE WE V...

Page 179: ...for auto programming and auto erasing and normal termination can be confirmed by reading the FO7 signal In status read mode error information is output if an error occurs Table 6 10 Settings for Oper...

Page 180: ...re required for command writing by means of a simultaneous 128 byte write 2 In memory read mode the number of cycles depends on the number of address write cycles n 6 8 4 Memory Read Mode 1 After the...

Page 181: ...tnxtc 20 s CE hold time tceh 0 ns CE setup time tces 0 ns Data hold time tdh 50 ns Data setup time tds 50 ns Write pulse width twep 70 ns WE rise time tr 30 ns WE fall time tf 30 ns CE ADDRESS DATA H...

Page 182: ...write cycle tnxtc 20 s CE hold time tceh 0 ns CE setup time tces 0 ns Data hold time tdh 50 ns Data setup time tds 50 ns Write pulse width twep 70 ns WE rise time tr 30 ns WE fall time tf 30 ns CE AD...

Page 183: ...time tce 150 ns OE output delay time toe 150 ns Output disable delay time tdf 100 ns Data output hold time toh 5 ns CE ADDRESS DATA VIL VIL VIH OE WE tacc toh toh tacc ADDRESS STABLE ADDRESS STABLE DA...

Page 184: ...ommand write cycle tnxtc 20 s CE hold time tceh 0 ns CE setup time tces 0 ns Data hold time tdh 50 ns Data setup time tds 50 ns Write pulse width twep 70 ns Status polling start time twsts 1 ms Status...

Page 185: ...3 The lower 8 bits of the transfer address must be H 00 or H 80 If a value other than a valid address is input processing will switch to a memory write operation but a write error will be flagged 4 Me...

Page 186: ...setup time tds 50 ns Write pulse width twep 70 ns Status polling start time tests 1 ms Status polling access time tspa 150 ns Memory erase time terase 100 40000 ms WE rise time tr 30 ns WE fall time t...

Page 187: ...eading is possible by enabling CE and OE 6 8 7 Status Read Mode 1 Status read mode is used to identify what type of abnormal end has occurred Use this mode when an abnormal end occurs in auto program...

Page 188: ...id address error Initial value 0 0 0 0 0 0 0 0 Indications Normal end 0 Abnormal end 1 Command error 1 Otherwise 0 Programming error 1 Otherwise 0 Erase error 1 Otherwise 0 Count exceeded 1 Otherwise...

Page 189: ...not in auto program mode or auto erase mode the FWE input pin should be driven low Don t care Don t care Figure 6 24 Oscillation Stabilization Time Writer Mode Setup and Power Down Sequence 6 8 10 Not...

Page 190: ...er failure and subsequent recovery Failure to do so may result in overprogramming or overerasing due to MCU runaway and loss of normal memory cell operation 3 FWE application disconnection FWE applica...

Page 191: ...n flash memory Clear the SWE bit before executing a program or reading data in flash memory When the SWE bit is set data in flash memory can be rewritten but flash memory should only be accessed for v...

Page 192: ...e to the mask ROM versions The values read from the internal registers for the flash ROM or the mask ROM version and F ZTAT version differ as follows Status Register Bit F ZTAT Version Mask ROM Versio...

Page 193: ...oth byte data and word data Note that the H8 3854 flash memory and mask ROM versions have different ROM and RAM sizes 7 1 1 Block Diagram Figure 7 1 shows a block diagram of the on chip RAM H FF7E H F...

Page 194: ...7 RAM Rev 3 00 Jul 19 2007 page 168 of 532 REJ09B0397 0300...

Page 195: ...addition both group have an I O port capable of interfacing with the on chip LCD controller H8 3857 Group port functions are listed in table 8 1 a and H8 3854 Group port functions in table 8 1 b Each...

Page 196: ...MR2 High current port P20 IRQ4 ADTRG External interrupt 4 and A D converter external trigger PMR2 AMR Port 3 8 bit I O port P37 to P33 None Input pull up MOS option High current port P32 SO1 P31 SI1 P...

Page 197: ...o P21 None Open drain output option High current port P20 IRQ4 ADTRG External interrupt 4 and A D converter external trigger PMR2 AMR Port 4 1 bit input only port P43 IRQ0 External interrupt 0 PMR2 3...

Page 198: ...54 Group 8 2 1 Overview Port 1 is an 8 bit I O port The H8 3857 Group port 1 pin configuration is shown in figure 8 1 a and the H8 3854 Group port 1 pin configuration in figure 8 1 b P1 IRQ TMIF P1 IR...

Page 199: ...egister that stores data for pins P17 through P10 If port 1 is read while PCR1 bits are set to 1 the values stored in PDR1 are read regardless of the actual pin states If port 1 is read while PCR1 bit...

Page 200: ...The settings in PCR1 and in PDR1 are valid only when the corresponding pin is designated in PMR1 as a general I O pin Upon reset PCR1 is initialized to H 00 PCR1 is a write only register All bits are...

Page 201: ...orresponding pin while clearing the bit to 0 turns off the MOS pull up Upon reset PUCR1 is initialized to H 00 H8 3857 Group Bit 7 6 5 4 3 2 1 0 PUCR17 PUCR16 PUCR15 PUCR14 PUCR13 PUCR12 PUCR11 PUCR10...

Page 202: ...7 IRQ3 TMIF Pin Function Switch IRQ3 This bit selects whether pin P17 IRQ3 TMIF is used as P17 or as IRQ3 TMIF Bit 7 IRQ3 Description 0 Functions as P17 I O pin initial value 1 Functions as IRQ3 TMIF...

Page 203: ...PWM Pin Function Switch PWM This bit selects whether pin P14 PWM is used as P14 or as PWM Bit 4 PWM Description 0 Functions as P14 I O pin initial value 1 Functions as PWM output pin In the H8 3854 Gr...

Page 204: ...tions and Selection Method P17 IRQ3 TMIF The pin function depends on bit IRQ3 in PMR1 bits CKSL2 to CKSL0 in TCRF and bit PCR17 in PCR1 IRQ3 0 1 PCR17 0 1 CKSL2 to CKSL0 Not 0 0 Pin function P17 input...

Page 205: ...t PCR14 in PCR1 PWM 0 1 PCR14 0 1 Pin function P14 input pin P14 output pin PWM output pin P13 The pin function depends on bit PCR13 in PCR1 PCR13 0 1 Pin function P13 input pin P13 output pin P12 TMO...

Page 206: ...B2 to TMB0 in TMB and bit PCR15 in PCR1 IRQ1 0 1 PCR15 0 1 TMB2 to TMB0 Not 111 111 Pin function P15 input pin P15 output pin IRQ1 input pin IRQ1 TMIB input pin Note When using as TMIB input pin clear...

Page 207: ...M P13 P12 TMOFH P11 TMOFL P10 TMOW High impedance Retains previous state Retains previous state High impedance Retains previous state Functional Functional Note A high level signal is output when the...

Page 208: ...Don t care Notes H8 3857 Group n 7 to 0 H8 3854 Group n 7 5 2 to 0 8 3 Port 2 Some port 2 functions differ between the H8 3857 Group and the H8 3854 Group The UD function multiplexed with the P21 pin...

Page 209: ...ort control register 2 PCR2 W H 00 H FFE5 Port mode register 2 PMR2 R W H C0 H FFC9 Port mode register 4 PMR4 R W H 00 H FFCB Port Data Register 2 PDR2 Bit 7 6 5 4 3 2 1 0 P27 P26 P25 P24 P23 P22 P21...

Page 210: ...PMR2 as a general I O pin Upon reset PCR2 is initialized to H 00 PCR2 is a write only register All bits are read as 1 Port Mode Register 2 PMR2 PMR2 is an 8 bit read write register controlling the se...

Page 211: ...the P32 SO1 pin output buffer Bit 2 POF1 Description 0 CMOS output initial value 1 NMOS open drain output In the H8 3854 Group bit 2 is reserved and must always be cleared to 0 Bit 1 P21 UD Pin Funct...

Page 212: ...ite R W R W R W R W R W R W R W R W PMR4 is an 8 bit read write register used to select CMOS output or NMOS open drain output for each port 2 pin Upon reset PMR4 is initialized to H 00 Bit n NMOS Open...

Page 213: ...bit settings in PCR2 PCR2n 0 1 Pin function P2n input pin P2n output pin Note n 7 to 2 P21 UD The pin function depends on bit UD in PMR2 and bit PCR21 in PCR2 UD 0 1 PCR21 0 1 Pin function P21 input...

Page 214: ...bit IEN4 in IENR1 to 0 disabling IRQ4 interrupts Legend Don t care 8 3 4 Pin States H8 3857 Group port 2 pin states in each operating mode are shown in table 8 7 a and H8 3854 Group port 2 pin states...

Page 215: ...figure 8 3 P3 P3 P3 P3 P3 P3 SO P3 SI P3 SCK 7 6 5 4 3 2 1 0 Port 3 1 1 1 Figure 8 3 Port 3 Pin Configuration 8 4 2 Register Configuration and Description Table 8 8 shows the port 3 register configura...

Page 216: ...s an 8 bit register for controlling whether each of the port 3 pins P37 to P30 functions as an input pin or output pin Setting a PCR3 bit to 1 makes the corresponding pin an output pin while clearing...

Page 217: ...hould always be cleared to 0 Bit 2 P32 SO1 Pin Function Switch SO1 This bit selects whether pin P32 SO1 is used as P32 or as SO1 Bit 2 SO1 Description 0 Functions as P32 I O pin initial value 1 Functi...

Page 218: ...e n 7 to 3 P32 SO1 The pin function depends on bit SO1 in PMR3 and bit PCR32 in PCR3 SO1 0 1 PCR32 0 1 Pin function P32 input pin P32 output pin SO1 output pin P31 SI1 The pin function depends on bit...

Page 219: ...previous state High impedance Retains previous state Functional Functional Note A high level signal is output when the MOS pull up is in the on state 8 4 5 MOS Input Pull Up Port 3 has a built in MOS...

Page 220: ...and a 1 bit input port and is configured as shown in figure 8 4 P4 IRQ P4 TXD P4 RXD P4 SCK 3 2 1 0 Port 4 3 0 Figure 8 4 Port 4 Pin Configuration 8 5 2 Register Configuration and Description Table 8...

Page 221: ...ates are read The pin state is always read from bit 3 P43 Upon reset PDR4 is initialized to H F8 Port Control Register 4 PCR4 Bit 7 6 5 4 3 2 1 0 PCR42 PCR41 PCR40 Initial value 1 1 1 1 1 0 0 0 Read W...

Page 222: ...TXD The pin function depends on bit TE in SCR3 and bit PCR42 in PCR4 TE 0 1 PCR42 0 1 Pin function P42 input pin P42 output pin TXD output pin P41 RXD The pin function depends on bit RE in SCR3 and b...

Page 223: ...RQ0 P42 TXD P41 RXD P40 SCK3 High impedance Retains previous state Retains previous state High impedance Retains previous state Functional Functional 8 6 Port 5 Port 5 functions are common to the H8 3...

Page 224: ...egister that stores data for port 5 pins P57 to P50 If port 5 is read while PCR5 bits are set to 1 the values stored in PDR5 are read regardless of the actual pin states If port 5 is read while PCR5 b...

Page 225: ...e corresponding pin while clearing the bit to 0 turns off the MOS pull up Upon reset PUCR5 is initialized to H 00 Port Mode Register 5 PMR5 Bit 7 6 5 4 3 2 1 0 WKP7 WKP6 WKP5 WKP4 WKP3 WKP2 WKP1 WKP0...

Page 226: ...mode Table 8 16 Port 5 Pin States Pins Reset Sleep Subsleep Standby Watch Subactive Active P57 WKP7 to P50 WKP0 High impedance Retains previous state Retains previous state High impedance Retains prev...

Page 227: ...9 pin configuration is shown in figure 8 6 P95 P96 P97 P90 P94 Note Dotted lines indicate connections inside the chip P93 P92 P91 Port 9 LCD controller DB5 DB6 DB7 DB0 DB4 DB3 DB2 DB1 Figure 8 6 Port...

Page 228: ...5 4 3 2 1 0 PCR97 PCR96 PCR95 PCR94 PCR93 PCR92 PCR91 PCR90 Initial value 0 0 0 0 0 0 0 0 Read Write W W W W W W W W PCR9 is an 8 bit register for controlling whether each of the port 9 pins P97 to P9...

Page 229: ...state Retains previous state High impedance Retains previous state Functional Functional 8 8 Port A Chip Internal I O port Port A functions are common to the H8 3857 Group and H8 3854 Group 8 8 1 Ove...

Page 230: ...port A pins PA3 to PA0 If port A is read while PCRA bits are set to 1 the values stored in PDRA are read If port A is read while PCRA bits are cleared to 0 the pin states are read Upon reset PDRA is...

Page 231: ...n function depends on the corresponding bit in PCRA PCRAn 0 1 Pin function PAn input pin PAn output pin Note n 3 to 0 8 8 4 Pin States Table 8 22 shows the port A pin states in each operating mode Tab...

Page 232: ...the H8 3854 Group 8 9 1 Overview Port B is an 8 bit input only port The H8 3857 Group port B pin configuration is shown in figure 8 8 a and the H8 3854 Group port B pin configuration in figure 8 8 b...

Page 233: ...H FFDE Port Data Register B PDRB Reading PDRB always gives the pin states However if a port B pin is selected as an analog input channel for the A D converter by AMR bits CH3 to CH0 that pin reads 0 r...

Page 234: ...8 I O Ports Rev 3 00 Jul 19 2007 page 208 of 532 REJ09B0397 0300...

Page 235: ...hoice of 4 overflow periods 8 bit timer Clock output 4 to 32 W 4 to W 32 8 choices TMOW Timer B 8 bit timer Interval timer Event counter 4 to 8192 7 choices TMIB Timer C 1 8 bit timer Interval timer E...

Page 236: ...m the system clock can be output at the TMOW pin Features Features of timer A are given below Choice of eight internal clock sources 8192 4096 2048 512 256 128 32 8 Choice of four overflow periods 1 s...

Page 237: ...W Legend TMA TCA IRRTA PSW PSS Note Can be selected only when the prescaler W output W 128 is used as the TCA input clock Timer mode register A Timer counter A Timer A overflow interrupt request flag...

Page 238: ...0 1 0 0 0 0 Read Write R W R W R W R W R W R W R W TMA is an 8 bit read write register for selecting the prescaler input clock and output clock Upon reset TMA is initialized to H 10 Bits 7 to 5 Clock...

Page 239: ...S 8 1 0 0 0 PSW 1 s Clock time base 1 PSW 0 5 s 1 0 PSW 0 25 s 1 PSW 0 03125 s 1 0 0 PSW and TCA are reset 1 1 0 1 Timer Counter A TCA Bit 7 6 5 4 3 2 1 0 TCA7 TCA6 TCA5 TCA4 TCA3 TCA2 TCA1 TCA0 Initi...

Page 240: ...arts counting up again In this mode timer A functions as an interval timer that generates an overflow output at intervals of 256 input clock pulses Note For details on interrupts see section 3 3 Inter...

Page 241: ...se function is selected as the internal clock of TCA in active mode or sleep mode the internal clock is not synchronous with the system clock so it is synchronized by a synchronizing circuit This may...

Page 242: ...e 9 2 Block Diagram of Timer B Pin Configuration Table 9 5 shows the timer B pin configuration Table 9 5 Pin Configuration Name Abbr I O Function Timer B event input TMIB Input Event input to TCB Regi...

Page 243: ...d Bits Bits 6 to 3 are reserved they always read 1 and cannot be modified Bits 2 to 0 Clock Select TMB2 to TMB0 Bits 2 to 0 select the clock input to TCB For external event counting either the rising...

Page 244: ...register 2 IRR2 is set to 1 TCB is allocated to the same address as timer load register B TLB Upon reset TCB is initialized to H 00 Timer Load Register B TLB Bit 7 6 5 4 3 2 1 0 TLB7 TLB6 TLB5 TLB4 TL...

Page 245: ...on 3 3 Interrupts Auto Reload Timer Operation Setting bit TMB7 in TMB to 1 causes timer B to function as an 8 bit auto reload timer When a reload value is set in TLB the same value is loaded into TCB...

Page 246: ...view Timer C is an 8 bit timer that increments or decrements each time a clock pulse is input This timer has two operation modes interval and auto reload Timer C is a function of the H8 3857 Group onl...

Page 247: ...terrupt request flag Prescaler S UD PSS TMIC W 4 TMC TCC TLC IRRTC Internal data bus Figure 9 3 Block Diagram of Timer C Pin Configuration Table 9 8 shows the timer C pin configuration Table 9 8 Pin C...

Page 248: ...d input clock Upon reset TMC is initialized to H 18 Bit 7 Auto Reload Function Select TMC7 Bit 7 selects whether timer C is used as an interval timer or auto reload timer Bit 7 TMC7 Description 0 Inte...

Page 249: ...EGR See section 3 3 2 Interrupt Control Registers for details on the IRQ edge select register Be sure to set bit IRQ2 in port mode register 1 PMR1 to 1 before setting bits TMC2 to TMC0 to 111 Timer Co...

Page 250: ...functions as an 8 bit interval timer Upon reset timer counter C TCC is initialized to H 00 and TMC to H 18 After a reset the counter continues uninterrupted incrementing as an interval up counter The...

Page 251: ...reload mode TMC7 1 when a new value is set in TLC the TLC value is also set in TCC Event Counter Operation Timer C can operate as an event counter counting an event signal input at pin TMIC External e...

Page 252: ...al clock must be selected The counter will not operate in these modes if another clock is selected If the internal W 4 clock is selected when W 8 is being used as the subclock SUB the lower 2 bits of...

Page 253: ...tial value of the toggle output can be set Counter can be reset by the compare match signal Two interrupt sources counter overflow and compare match Timer FL 8 bit timer event counter Choice of four i...

Page 254: ...Legend TCRF TCSRF TCFH TCFL OCRFH OCRFL IRRTFH IRRTFL PSS Timer control register F Timer control status register F 8 bit timer counter FH 8 bit timer counter FL Output compare register FH Output compa...

Page 255: ...12 Timer F Registers Name Abbr R W Initial Value Address Timer control register F TCRF W H 00 H FFB6 Timer control status register F TCSRF R W H 00 H FFB7 8 bit timer counter FH TCFH R W H 00 H FFB8 8...

Page 256: ...made in bit CCLRH in TCSRF When TCF overflows from H FFFF to H 0000 the overflow flag OVFH in TCSRF is set to 1 If bit OVIEH in TCSRF is set to 1 when an overflow occurs bit IRRTFH in interrupt reques...

Page 257: ...ected by clearing bit CKSH2 to 0 in timer control register F TCRF The OCRF contents are always compared with the 16 bit timer counter TCF When the contents match the compare match flag CMFH in TCSRF i...

Page 258: ...put level at pin TMOFH The setting goes into effect immediately after this bit is written Bit 7 TOLH Description 0 Low level initial value 1 High level Bits 6 to 4 Clock Select H CKSH2 to CKSH0 Bits 6...

Page 259: ...r 1 PMR1 from 0 to 1 or from 1 to 0 while the TMIF pin is at the low level may cause the timer F counter to be incremented Timer Control Status Register F TCSRF Bit 7 6 5 4 3 2 1 0 OVFH CMFH OVIEH CCL...

Page 260: ...nter Clear H CCLRH In 16 bit mode bit 4 selects whether or not TCF is cleared when a compare match occurs between TCF and OCRF In 8 bit mode bit 4 selects whether or not TCFH is cleared when a compare...

Page 261: ...ing by compare match disabled initial value 1 TCFL clearing by compare match enabled 9 5 3 Interface with the CPU TCF and OCRF are 16 bit read write registers whereas the data bus between the CPU and...

Page 262: ...e Bus interface CPU H 55 TEMP H AA TCFH H AA TCFL H 55 Internal data bus Lower byte write Figure 9 5 TCF Write Operation CPU TCF Read Access When the upper byte of TCF is read the upper byte data is s...

Page 263: ...ad the lower byte data is sent directly to the CPU Figure 9 6 shows a TCF read operation when H AAFF is read from TCF CPU H AA TEMP H FF TCFH H AA TCFL H FF Internal data bus Upper byte read Bus inter...

Page 264: ...perating clock by bits CKSL2 to CKSL0 in TCRF TCF is continuously compared with the contents of OCRF When these two values match the CMFH bit in TCSRF is set to 1 At this time if IENTFH of IENR2 is 1...

Page 265: ...f the clock input can be counted The edge of an external event is selected by bit IEG3 in the interrupt controller s IEGR register An external event pulse width of at least two system clock cycles is...

Page 266: ...operation 16 bit timer mode The output at pin TMOFH toggles when all 16 bits match and a compare match signal is generated If the compare match signal occurs at the same time as new data is written i...

Page 267: ...tion however the new value written in bit TOLL will be output at pin TMOFL If an OCRFL write occurs at the same time as a compare match signal the compare match signal is inhibited If a compare match...

Page 268: ...Prescaler S Timer mode register W Figure 9 8 Block Diagram of Watchdog Timer Register Configuration Table 9 14 shows the watchdog timer register configuration These registers are valid only in the F Z...

Page 269: ...eration status Bit 7 Bit 6 Write Inhibit B6WI Bit 7 controls writing of data to bit 6 of TCSRW Bit 7 B6WI Description 0 Writing to bit 6 is enabled 1 Writing to bit 6 is disabled initial value This bi...

Page 270: ...o this bit Bit 2 Watchdog Timer On WDON Bit 2 controls watchdog timer operation Bit 2 WDON Description 0 Watchdog timer operation is disabled initial value Clearing condition In a reset or when 0 is w...

Page 271: ...r Counter W TCW TCW7 TCW2 TCW1 TCW0 TCW6 TCW5 TCW4 TCW3 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W Bit Initial value Read Write TCW is an 8 bit read write up counter that is incre...

Page 272: ...counter that increments with each input clock pulse If 1 is written to WDON while writing 0 to B2WI when TCSRWE in TCSRW is set to 1 TCW begins counting up When a clock pulse is input after the TCW co...

Page 273: ...TCW Reset generated Start 512 osc clock cycles Figure 9 9 Example of Watchdog Timer Operation 9 6 4 Watchdog Timer Operating Modes Watchdog timer operating modes are shown in table 9 15 Table 9 15 Wa...

Page 274: ...9 Timers Rev 3 00 Jul 19 2007 page 248 of 532 REJ09B0397 0300...

Page 275: ...ice of 8 bit or 16 bit data length Continuous clock output Choice of 8 internal clocks 1024 to 2 or external clock Open drain output possible Interrupt requested at completion of transfer SCI3 Synchro...

Page 276: ...I1 performs synchronous serial transfer of 8 bit or 16 bit data SCI1 is a function of the H8 3857 Group only and is not provided in the H8 3854 Group Features Features of SCI1 are as follows Choice of...

Page 277: ...f SCI1 SCK1 SI1 SO1 SCR1 SCSR1 SDRU SDRL PSS Transfer bit counter Transmit receive control circuit Internal data bus Legend SCR1 SCSR1 SDRU SDRL IRRS1 PSS Serial control register 1 Serial control stat...

Page 278: ...isters Name Abbr R W Initial Value Address Serial control register 1 SCR1 R W H 00 H FFA0 Serial control status register 1 SCSR1 R W H 80 H FFA1 Serial data register U SDRU R W Undefined H FFA2 Serial...

Page 279: ...are reserved they should always be cleared to 0 Bit 3 Clock Source Select 3 CKS3 Bit 3 selects the clock source and sets pin SCK1 as an input or output pin Bit 3 CKS3 Description 0 Clock source is pre...

Page 280: ...Data Bit SOL Bit 6 sets the SO1 output level When read SOL returns the output level at the SO1 pin After completion of a transmission SO1 continues to output the value of the last bit of transmitted d...

Page 281: ...ey are always read as 0 and cannot be modified Bit 1 Reserved Bit Bit 1 is reserved it should always be cleared to 0 Bit 0 Start Flag STF Bit 0 controls the start of a transfer Setting this bit to 1 c...

Page 282: ...16 bit transfer SDRU is used for the upper 8 bits In 8 bit transfer data written to SDRL is output from pin SO1 starting from the least significant bit LSB This data is than replaced by LSB first dat...

Page 283: ...or 16 bit synchronous transfer mode Select the serial clock in bits CKS3 to CKS0 Writing data to SCR1 initializes the internal state of SCI1 Write transmit data in SDRL and SDRU as follows 8 bit trans...

Page 284: ...ied out as follows Set bits SO1 SI1 and SCK1 in PMR3 to 1 so that the respective pins function as SO1 SI1 and SCK1 If necessary set bit POF1 in port mode register 2 PMR2 for NMOS open drain output at...

Page 285: ...is set to 1 SCI1 interrupt requests can be enabled or disabled by bit IENS1 of interrupt enable register 1 IENR1 For further details see section 3 3 Interrupts 10 2 5 Application Notes Note the follow...

Page 286: ...two or more other processors using the multiprocessor communication function There are twelve selectable serial data communication formats Data length seven or eight bits Stop bit length one or two bi...

Page 287: ...I3 SCK TXD RXD 3 TSR RSR RDR TDR SSR SCR3 SMR BRR BRC External clock Baud rate generator Internal clock 64 16 4 Clock Transmit receive control Internal data bus Interrupt requests TEI TXI RXI ERI Lege...

Page 288: ...figuration Table 10 5 shows the SCI3 internal register configuration Table 10 5 SCI3 Registers Name Abbr R W Initial Value Address Serial mode register SMR R W H 00 H FFA8 Bit rate register BRR R W H...

Page 289: ...s transferred from the receive shift register RSR to RDR completing a receive operation Thereafter RSR again becomes ready to receive new data RSR and RDR form a double buffer mechanism that allows da...

Page 290: ...inuous transmission TDR can be read or written by the CPU at all times TDR is initialized to H FF upon reset or in standby mode watch mode subactive mode or subsleep mode Serial Mode Register SMR Bit...

Page 291: ...n parity is added to transmit data depending on the setting of the parity mode bit PM When data is received it is checked for odd or even parity as designated in bit PM Bit 4 Parity Mode PM In asynchr...

Page 292: ...t character Bit 2 Multiprocessor Mode MP Bit 2 enables or disables the multiprocessor communication function When the multiprocessor communication function is enabled the parity enable PE and parity m...

Page 293: ...ansmit data register empty bit TDRE in the serial status register SSR is set to 1 The TXI interrupt can be cleared by clearing bit TDRE to 0 or by clearing bit TIE to 0 Bit 7 TIE Description 0 Transmi...

Page 294: ...in Notes 1 When RE is cleared to 0 this has no effect on the SSR flags RDRF FER PER and OER which retain their states 2 Serial data receiving begins when in this state a start bit is detected in async...

Page 295: ...1 and 0 select the clock source and enable or disable clock output at pin SCK3 The combination of bits CKE1 and CKE0 determines whether pin SCK3 is a general I O port a clock output pin or a clock inp...

Page 296: ...o 0 it is first necessary to read a 1 Bit 2 TEND and bit 1 MPBR are read only bits and cannot be modified SSR is initialized to H 84 upon reset or in standby mode watch mode subactive mode or subsleep...

Page 297: ...evious states An overrun error OER occurs if receiving of data is completed while bit RDRF remains set to 1 If this happens receive data will be lost Bit 5 Overrun Error OER Bit 5 is a status flag ind...

Page 298: ...transferred to RDR but RDRF is not set While FER is set to 1 data receiving cannot be continued In synchronous mode data transmitting cannot be continued either Bit 3 Parity Error PER Bit 3 is a statu...

Page 299: ...ve MPBR Bit 1 holds the multiprocessor bit in data received in asynchronous mode using a multiprocessor format MPBR is a read only bit and cannot be modified Bit 1 MPBR Description 0 Indicates recepti...

Page 300: ...ed to H FF upon reset or in standby mode watch mode subactive mode or subsleep mode Table 10 6 gives examples of how BRR is set in asynchronous mode The values in table 10 6 are for active high speed...

Page 301: ...0 26 1 212 0 03 2 64 0 70 2 70 0 03 150 1 127 0 1 155 0 16 1 191 0 1 207 0 16 300 0 255 0 1 77 0 16 1 95 0 1 103 0 16 600 0 127 0 0 155 0 16 0 191 0 0 207 0 16 1200 0 63 0 0 77 0 16 0 95 0 0 103 0 16...

Page 302: ...0 0 3 0 0 3 1 73 Notes 1 Settings should be made so that error is within 1 2 BRR setting values are derived by the following equation N 106 1 OSC 64 22n B B Bit rate bits s N BRR baud rate generator s...

Page 303: ...1 0 3 64 1 1 Table 10 8 shows the maximum bit rate for selected frequencies in asynchronous mode Values in table 10 8 are for active high speed mode Table 10 8 Maximum Bit Rate at Selected Frequencie...

Page 304: ...249 2 124 1 K 0 249 1 124 1 249 2 5 K 0 99 0 199 1 99 1 124 5 K 0 49 0 99 0 199 0 249 10 K 0 24 0 49 0 99 0 124 25 K 0 9 0 19 0 39 0 49 50 K 0 4 0 9 0 19 0 24 100 K 0 4 0 9 250 K 0 0 0 1 0 3 0 4 500 K...

Page 305: ...ock source is determined by bit COM in SMR and bits CKE1 and CKE0 in serial control register 3 SCR3 as shown in table 10 12 Asynchronous Mode Data length choice of 7 bits or 8 bits Options include add...

Page 306: ...baud rate generator is not used Operation is synchronous with the input clock Table 10 11 SMR Settings and SCI3 Communication Format SMR Setting Communication Format Bit 7 COM Bit 6 CHR Bit 2 MP Bit 5...

Page 307: ...OM Bit 1 CKE1 Bit 0 CKE0 Mode Clock Source Pin SCK3 Function 0 0 0 Asynchronous Internal I O port SCK3 function not used 1 mode Outputs clock with same frequency as bit rate 1 0 External Clock should...

Page 308: ...een completely received in RSR TXI TDRE TIE When TSR empty previous trans mission complete is detected and the transmit data set in TDR is transferred to TSR TDRE is set to 1 If TIE is 1 at this time...

Page 309: ...upt 10 3 4 Operation in Asynchronous Mode In asynchronous communication mode a start bit indicating the start of communication and a stop bit indicating the end of communication are added to each char...

Page 310: ...monitors the communication line and begins serial data communication when it detects a space low level signal which is regarded as a start bit One character consists of a start bit low level transmit...

Page 311: ...12 0 0 0 0 S 8 bit data STOP 0 0 0 1 S 8 bit data STOP STOP 0 1 0 0 S 8 bit data P STOP 0 1 0 1 S 8 bit data P STOP STOP 1 0 0 0 S 7 bit data STOP 1 0 0 1 S 7 bit data STOP STOP 1 1 0 0 S 7 bit data P...

Page 312: ...al data 1 character 1 frame 0 D0 D1 D2 D3 D4 D5 D6 D7 0 1 1 1 Clock Figure 10 8 Phase Relation of Output Clock and Communication Data in Asynchronous Mode 8 Bit Data Parity Bit Added and 2 Stop Bits D...

Page 313: ...been set If clock output is selected for reception in synchronous mode a clock signal will be output as soon as bits CKE1 and CKE0 and bit RE are set to 1 Set the transmit receive format in the serial...

Page 314: ...End 1 2 3 1 2 3 Read the serial status register SRR and after confirming that bit TDRE 1 write transmit data in the transmit data register TDR When data is written to TDR TDRE is automatically cleared...

Page 315: ...nd after the stop bit is sent transmission of the next frame starts If TDRE is 1 the TEND bit in SSR is set to 1 and after the stop bit is sent the output remains at 1 mark state A TEI interrupt is re...

Page 316: ...ng A OER PER FER 1 RDRF 1 No Yes 2 Read the serial status register SSR and after confirming that bit RDRF 1 read received data from the receive data register RDR When RDR data is read RDRF is automati...

Page 317: ...bit RDRF is set to 1 and the received data is stored in RDR At that time if bit RIE in SCR3 is set to 1 an RXI interrupt is requested If the error check detects a receive error the appropriate error...

Page 318: ...igure 10 13 Typical Receive Operation in Asynchronous Mode 8 Bit Data Parity Bit Added and 1 Stop Bit 10 3 5 Operation in Synchronous Mode In synchronous mode data is sent or received in synchronizati...

Page 319: ...haracter of data starts from the LSB and ends with the MSB The communication line retains the MSB state after the MSB is output In synchronous receive mode SCI3 latches receive data in synchronization...

Page 320: ...Continue data transmission Read bit TEND in SSR TEND 1 Write 0 to bit TE in SCR3 End No Yes No Yes No Yes 1 2 1 2 Read the serial status register SSR and after confirming that bit TDRE 1 write transmi...

Page 321: ...t 7 is being transmitted If TDRE is 0 data is transferred from TDR to TSR and after the MSB bit 7 is sent transmission of the next frame starts If TDRE is 1 the TEND bit in SSR is set to 1 and after t...

Page 322: ...matically cleared to 0 1 Read bit OER in the serial status register SSR to determine if an error has occurred If an overrun error has occurred overrun error processing is executed To continue receivin...

Page 323: ...ed If an overrun error is detected OER is set to 1 and RDRF remains set to 1 Then if bit RIE in SCR3 is set to 1 an ERI interrupt is requested For the overrun error detection conditions and receive da...

Page 324: ...the receive data register RDR When data is read from RDR RDRF is automatically cleared to 0 To continue transmitting and receiving serial data read bit RDRF and finish reading RDR before the MSB bit...

Page 325: ...ving processor is addressed by an ID code A serial communication cycle consists of two cycles an ID sending cycle that identifies the receiving processor and a data sending cycle The ID sending cycle...

Page 326: ...a sent to receiving processor designated by ID ID 01 ID 02 ID 03 ID 04 H 01 H AA MPB 1 MPB 0 MPB Multiprocessor bit Figure 10 20 Example of Interprocessor Communication Using Multiprocessor Format Dat...

Page 327: ...2 3 2 3 1 To continue transmitting data read bit TDRE to make sure it is set to 1 then write the next data to TDR When data is written to TDR TDRE is automatically cleared to 0 To output a break signa...

Page 328: ...op bit is being transmitted If TDRE is 0 data is transferred from TDR to TSR and after the stop bit is sent transmission of the next frame starts If TDRE is 1 the TEND bit in SSR is set to 1 and after...

Page 329: ...executed Read SSR check that bit RDRF 1 then read received data from the receive data register RDR If a receive error occurs read bits OER and FER in SSR to determine which error occurred After the n...

Page 330: ...D7 0 1 1 0 1 Start bit Stop bit Stop bit Start bit Receive data ID2 Receive data data 2 Mark idle state MPB MPB MPB MPB MPIE RDRF RDR value ID1 b Data matches own ID 1 frame 1 frame 1 frame 1 frame ID...

Page 331: ...ring data transmission The initial value of bit TDRE is 1 Accordingly if the transmit data empty interrupt request TXI is enabled by setting bit TIE to 1 in SCR3 before placing transmit data in TDR TX...

Page 332: ...lags in SSR are set as shown in table 10 17 If an overrun error occurs data is not transferred from RSR to RDR and receive data is lost Table 10 17 SSR Status Flag States and Transfer of Receive Data...

Page 333: ...e TXD pin becomes an output port outputting the value 0 Receive Error Flags and Transmit Operation Sysnchronous Mode Only When a receive error flag OER PER or FER is set to 1 SCI3 will not start trans...

Page 334: ...below When D 0 5 and F 0 M 0 5 1 2 16 100 46 875 Equation 2 This value is theoretical In actual system designs a margin of from 20 to 30 percent should be allowed Relationship between Bit RDRF and Rea...

Page 335: ...chronous mode or before the stop bit is transferred in asynchronous mode Caution on Switching of SCK3 Function If pin SCK3 is used as a clock output pin by SCI3 in synchronous mode and is then switche...

Page 336: ...to 1 and 0 respectively b Clear bit COM in SMR to 0 c Clear bits CKE1 and CKE0 in SCR3 to 0 Note that special care is also needed here to avoid an intermediate level of voltage from being applied to S...

Page 337: ...ures of the 14 bit PWM are as follows Choice of two conversion periods A conversion period of 32 768 with a minimum modulation width of 2 PWCR0 1 or a conversion period of 16 384 with a minimum modula...

Page 338: ...guration of the 14 bit PWM Table 11 2 Register Configuration Name Abbr R W Initial Value Address PWM control register PWCR W H FE H FFD0 PWM data register U PWDRU W H C0 H FFD1 PWM data register L PWD...

Page 339: ...Write W W W W W W Bit 7 6 5 4 3 2 1 0 PWDRL PWDRL7 PWDRL6 PWDRL5 PWDRL4 PWDRL3 PWDRL2 PWDRL1 PWDRL0 Initial value 0 0 0 0 0 0 0 0 Read Write W W W W W W W W PWDRU and PWDRL form a 14 bit write only re...

Page 340: ...with internal signals One conversion period consists of 64 pulses as shown in figure 11 2 The total of the high level pulse widths during this period TH corresponds to the data in PWDRU and PWDRL This...

Page 341: ...maximum number of analog input channels is eight in the H8 3857 Group and four in the H8 3854 Group 12 1 1 Features The A D converter has the following features 8 bit resolution Input channels 8 in H...

Page 342: ...D result register Control logic Com parator AN0 1 AN1 1 AN2 1 AN3 1 AN4 AN5 AN6 AN7 ADTRG AVCC 2 AVSS 2 Multiplexer Reference voltage IRRAD AVCC 2 AVSS 2 Notes 1 AN0 to AN3 are functions of the H8 38...

Page 343: ...4 Analog input pin 5 AN5 Input Analog input channel 5 Analog input pin 6 AN6 Input Analog input channel 6 Analog input pin 7 AN7 Input Analog input channel 7 External trigger input pin ADTRG Input Ex...

Page 344: ...is complete the conversion result is stored in ADRR as 8 bit data this data is held in ADRR until the next conversion operation starts ADRR is not cleared on reset 12 2 2 A D Mode Register AMR Bit 7...

Page 345: ...EGR See Interrupt Edge Select Register IEGR in section 3 3 2 Interrupt Control Registers for details Bits 5 and 4 Reserved Bits Bits 5 and 4 are reserved they are always read as 1 and cannot be modifi...

Page 346: ...edge of the external trigger signal which also sets ADSF to 1 When conversion is complete the converted data is set in the A D result register ADRR and at the same time ADSF is cleared to 0 Bit 7 A D...

Page 347: ...et to 1 If the conversion time or input channel needs to be changed in the A D mode register AMR during A D conversion bit ADSF should first be cleared to 0 stopping the conversion operation in order...

Page 348: ...D mode register AMR are set to 0101 making pin AN1 the analog input channel A D interrupts are enabled by setting bit IENAD to 1 and A D conversion is started by setting bit ADSF to 1 When A D convers...

Page 349: ...ersion 2 Idle Interrupt IRRAD IENAD ADSF Channel 1 AN 1 operation state ADRR Set Set Set Read conversion result Read conversion result A D conversion result 1 A D conversion result 2 A D conversion st...

Page 350: ...300 Start Set A D conversion speed and input channel Perform A D conversion End Yes No Disable A D conversion end interrupt Start A D conversion ADSF 0 No Yes Read ADSR Read ADRR data Figure 12 4 Flow...

Page 351: ...No Clear bit IRRAD to 0 in IRR2 Read ADRR data Perform A D conversion Figure 12 5 Flow Chart of Procedure for Using A D Converter 2 Interrupts Used 12 6 Application Notes Data in the A D result regis...

Page 352: ...12 A D Converter Rev 3 00 Jul 19 2007 page 326 of 532 REJ09B0397 0300...

Page 353: ...software heritability when using a combination of MPU and LCD driver This module operates on the subclock making it ideal for use in small portable devices 13 1 1 Features Built in bit mapped display...

Page 354: ...SEG41 Common counter Blink counter Blink start line register Blink end line register Display line counter Display start line register Address register Control register 1 2 Index register Frame freque...

Page 355: ...nput LCD bias setting LCD test pin V34 Input Internal resistance test pins shorted to V3 LCD step up capacitance connection pins C1 C1 C2 C2 For connection of external capacitances for LCD step up LCD...

Page 356: ...ter 1 LR0 W 1 0 0 0 0 Control register 2 LR1 W 1 Address register LR2 W 1 0 Frame frequency setting register LR3 W 1 Display data register LR4 R W 1 0 0 Display start line register LR5 W 1 Blink regis...

Page 357: ...ic display and drive duty selection Upon reset LR0 is initialized to H 00 Bits 7 and 6 Reserved Bits Bits 7 and 6 are reserved they should always be cleared to 0 Bit 5 Module Standby LSBY Bit 5 is the...

Page 358: ...l bits in one display memory data byte are output to the segment pins The X address that can be output is in the range H 0 to H 4 in the case of 1 32 duty H 0 to H 6 in the case of 1 16 duty and H 0 t...

Page 359: ...Setting DISP Bit 6 selects operation or halting of the LCD display When the LSBY bit in LR0 is set to 1 DISP is cleared Bit 6 DISP Description 0 LCD is turned off All LCD outputs go to the VSS level i...

Page 360: ...address to be incremented after the display memory access specified by the RMW bit The selected address is cleared after a display memory access with the maximum value for the valid display data area...

Page 361: ...y incremented after the access specified by the RMW bit in LR1 and is cleared after an access with the maximum value for the valid display data area When INC is 0 and YA4 to YA0 represent the maximum...

Page 362: ...00 Bits 7 and 6 Reserved Bits Bits 7 and 6 are reserved they should always be cleared to 0 Bits 5 to 0 Frame Frequency Setting FS5 to FS0 Bits 5 to 0 control the subclock division ratio and set the L...

Page 363: ...1 1 1 48 1 0 0 1 1 1 80 1 1 0 1 1 1 112 0 0 1 0 0 0 18 0 1 1 0 0 0 50 1 0 1 0 0 0 82 1 1 1 0 0 0 114 0 0 1 0 0 1 20 0 1 1 0 0 1 52 1 0 1 0 0 1 84 1 1 1 0 0 1 116 0 0 1 0 1 0 22 0 1 1 0 1 0 54 1 0 1 0...

Page 364: ...before being output to the bus After a reset the display memory and LR4 contents are undefined 13 2 7 Display Start Line Register LR5 7 6 5 4 ST4 0 W 3 ST3 0 W 0 ST0 0 W 2 ST2 0 W 1 ST1 0 W Bit Initia...

Page 365: ...on the value of the SOB bit in LR0 as shown below SOB BK7 BK6 BK5 BK4 BK3 BK2 BK1 BK0 0 SEG36 to SEG40 SEG31 to SEG35 SEG26 to SEG30 SEG21 to SEG25 SEG16 to SEG20 SEG11 to SEG15 SEG6 to SEG10 SEG1 to...

Page 366: ...s 7 to 5 Reserved Bits Bits 7 to 5 are reserved they should always be cleared to 0 Bits 4 to 0 Blink End Line Setting BEL4 to BEL0 Bits 4 to 0 specify the end line of an area made to blink Set a value...

Page 367: ...the contrast control resistance between the VLCD and V1 levels it is possible to adjust the contrast of the LCD panel The contrast control resistance can be set in the range from 0 1R to 1 6R where R...

Page 368: ...m display control the time etc can be constantly displayed As this module includes a built in 2X or 3X LCD power supply step up circuit an LCD system can be configured with just a few external parts r...

Page 369: ...RS Writing to Index Register When RS and R W are both cleared to 0 data DB7 to DB0 is written to the index register IR at the falling edge of STRB Do not change RS or R W at the fall of STRB Reading...

Page 370: ...utput Also LCD controller internal pins RS R W and STRB are input only pins and DB7 to DB0 input output is controlled by R W Therefore the following points must be noted 1 After reset release and stan...

Page 371: ...to 0 MOV B R0H PDR9 MOV B R0L PCR9 Output H 04 from port 9 MOV B R1H PDRA MOV B R1L PDRA Write H 04 to index register Read display data register MOV B R1L PCR9 Set port 9 to input mode MOV W H 0706 R...

Page 372: ...o COM16 SEG57 output common signal non selection waveforms COM17 SEG56 to COM24 SEG49 output the same waveforms as COM1 to COM8 and COM25 SEG48 to COM32 SEG41 output common signal non selection wavefo...

Page 373: ...SEG40 SEG1 to SEG40 SEG1 to SEG56 SEG1 to SEG56 SEG1 to SEG40 COM32 SEG41 to COM25 SEG48 Common signal non selection waveform COM16 to COM1 COM32 to COM17 COM32 to COM17 COM24 SEG49 to COM17 SEG56 COM...

Page 374: ...3 SEG4 SEG5 SEG40 COM1 COM2 0 1 0 1 0 1 0 1 0 1 H 00 H 01 DB7 MSB DB0 LSB SEG40 SEG56 SEG64 LCD Y address 2 SOB 1 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 1 0 1 0 1 0 COM1 COM2 0 1 0 1 0 1 0 1 0 1 H 00...

Page 375: ...r display mode SOB 0 in which only 5 bits of each display data byte can be output to perform efficient 5 dot 8 dot character output and a graphic display mode SOB 1 in which all the bits of a data byt...

Page 376: ...SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 1 Character display mode SOB 0 1 8 duty Display dots 320 H 00 H 07 H 08 H 0F H 10 H 1F H 00 H 05 H 06 H 07 Y address X addre...

Page 377: ...2 COM31 COM2 COM1 1 32 duty Display dots 1280 2 Graphic display mode SOB 1 H 00 H 07 H 08 H 0F H 10 H 1F H 00 H 05 H 06 H 07 Y address X address SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG3...

Page 378: ...COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 1 16 duty Display dots 896 H 00 H 07 H 08 H 0F H 10 H 1F H 00 H 05 H 06 H 07 Y address X address SEG1 SEG2 SEG3 SEG4 SE...

Page 379: ...e 13 6 for the procedure After the respective display data register LR4 accesses the X and Y addresses are automatically incremented on the basis of the value set in the INC bit in control register 2...

Page 380: ...a access INC 1 1 2 3 Address register LR2 bits XA2 to XA0 show the X address and bits YA4 to YA0 show the Y address X address operation 1 SOB 0 Address becomes H 0 after H 7 regardless of the display...

Page 381: ...r Display The LCD controller s display RAM is of the dual port type with accesses from the CPU and reads for LCD display independent of each other This allows flexible interfacing RS R W STRB Input da...

Page 382: ...ification Address 1 No Yes START END Figure 13 8 Read Modify Write Mode Flowchart 13 3 7 Scroll Function The LCD controller allows vertical scrolling of any number of lines to be performed by specifyi...

Page 383: ...e 0 H 01 H 02 H 03 H 04 H 05 H 06 H 07 H 08 H 09 H 0A H 0B H 0C H 0D H 0E H 0F H 00 Y address H 01 H 02 H 03 H 04 H 05 H 06 H 07 H 00 Y address Display start line 1 H 02 H 03 H 04 H 05 H 06 H 07 H 08...

Page 384: ...SOB 0 or 8 bit unit SOB 1 is set in the blink register LR6 When 1 is set in the blink register LR6 blinking of the corresponding dot is controlled After making these register settings blinking is sta...

Page 385: ...Rev 3 00 Jul 19 2007 page 359 of 532 REJ09B0397 0300 Display start line Blink start line Blink end line H 4 H 4 H 7 Display start line Blink start line Blink end line H 0 H 0 H 7 Figure 13 11 Blinkin...

Page 386: ...cedures for initiating and clearing module standby mode The initiation and clearing procedures must be followed exactly in order to protect the display memory contents When the CPU is placed in standb...

Page 387: ...hese procedures may result in an abnormal display Starting display Halting display Step up operation starts Note When the built in step up circuit is used wait for the step up circuit power supply to...

Page 388: ...ubclock is supplied Since Vci is also used for the step up circuit power supply an adequate current must be assured Step up cannot be performed below VCC Apply a Vci voltage that gives a VLOUT level b...

Page 389: ...in step up circuit and cut the built in op amp power supply The same potential as V1 should be input to VLCD Apply a voltage not exceeding VLCD to V2 through V5 The input level of VLCD and V1 must be...

Page 390: ...page 364 of 532 REJ09B0397 0300 V1 V2 V3 V4 V5 VSS V1 V2 V3 V4 V5 VSS V1 V2 V3 V4 V5 VSS V1 V2 V3 V4 V5 VSS V1 V2 V3 V4 V5 VSS COM1 COM2 COM32 1 frame Line selection period Not selected Selected SEG1...

Page 391: ...LCD controller includes bleeder resistances that generate levels V1 to V5 and voltage follower op amp circuits Set the OPON bit in control register 2 LR1 to 1 Contrast can be controlled by software u...

Page 392: ...SEG1 to SEG40 COM32 SEG41 to COM9 SEG64 COM1 to COM8 C1 Control circuit Step up circuit PWR 0 OPON 1 VSS 0 1 to 0 5 F Note Rt is a test resistance The V3 and V34 pins should be shorted VCC V1 R VR V2...

Page 393: ...ep up circuit and op amps are not used the OPON bit in control register 2 LR1 should be cleared to 0 V2OUT V3OUT V4OUT VSS V5OUT Vci V1OUT V3 V34 V4 SEG1 to SEG40 COM32 SEG41 to COM9 SEG64 COM1 to COM...

Page 394: ...be set to 1 Contrast can be controlled by software using the contrast control register LRA If the capacitance of the LCD panel to be driven is large capacitors of around 0 1 to 0 5 F should be inserte...

Page 395: ...ould not be lower than VCC and should not exceed 7 0 V With 3X step up in particular do not input a voltage of 2 3 V or above as the reference voltage Vci Vci is also used for the step up circuit powe...

Page 396: ...pins should be shorted The output voltage after step up should not be lower than VCC and should not exceed 7 0 V Vci is also used for the step up circuit power supply Use a transistor etc for current...

Page 397: ...ls can be supplied from external bleeder resistances In this case clear the OPON bit in control register 2 LR1 to 0 to turn the op amps off The built in contrast control circuit cannot be used so cont...

Page 398: ...ircuit reference voltage Vci The built in contrast control circuit cannot be used The output voltage after step up should not be lower than VCC and should not exceed 7 0 V With 3X step up in particula...

Page 399: ...own in table 13 7 To ensure stable operation of the voltage follower op amp circuits that output levels V1 to V5 the contrast control register LRA should be set so that the potential difference betwee...

Page 400: ...VLCD VSS VDR 0 976 VLCD VSS 13 3 15 LCD Drive Bias Selection Circuit The ideal bias value that gives the best contrast is calculated using the equation shown below If drive is performed at a bias valu...

Page 401: ...matrix display of up to 40 16 dots I O ports are used for the interface with the CPU offering excellent software heritability when using a combination of MPU and LCD driver This module operates on th...

Page 402: ...n counter Latch 2 Latch 1 40 16 bit display memory X decoder Display data register Y decoder MPX Display line counter Address register Index register Frame frequency setting register Control register...

Page 403: ...I O LCD drive power supply level input output pins 14 1 4 Register Configuration The LCD controller has one index register and five control registers all of which are accessed via an I O port interfa...

Page 404: ...reserved they should always be cleared to 0 Bits 2 to 0 Index Register IR2 to IR0 Bits 2 to 0 are used to select one of the LCD controller s five control registers The correspondence between the sett...

Page 405: ...t 1 Display Duty Select DDTY1 Bit 1 selects a display duty of 1 16 or 1 8 Bit 1 DDTY1 Description 0 1 16 duty selected initial value 1 1 8 duty selected Y address H 8 to H F display data is invalid Bi...

Page 406: ...ances is supplied When the LCD drive power supply level is applied to V1OUT through V5OUT from an external source LPS1 and LPS0 must be cleared to 0 When the LSBY bit in LR0 is set LPS1 and LPS0 are c...

Page 407: ...is an 8 bit write only register that sets the display memory X and Y direction addresses accessed by the CPU Upon reset LR2 is initialized to H 00 Bits 7 to 5 X Address Setting XA2 to XA0 Bits 7 to 5...

Page 408: ...cy Upon reset LR3 is initialized to H 00 Bits 7 to 3 Reserved Bits Bits 7 to 3 are reserved they should always be cleared to 0 Bits 2 to 0 Frame Frequency Setting FS2 to FS0 Bits 2 to 0 control the su...

Page 409: ...0 18 8 1 Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited 14 2 6 Display Data Register LR4 7 D7 Undefined R W 6 D6 Undefined R W 5 D5 Undefined R W 4 D4 U...

Page 410: ...a maximum of 40 16 dots As the LCD controller operates on the subclock to perform display control the time etc can be constantly displayed Also since data in the display RAM is retained even in module...

Page 411: ...RS Writing to Index Register When RS and R W are both cleared to 0 data DB7 to DB0 is written to the index register IR at the falling edge of STRB Do not change RS or R W at the fall of STRB Reading...

Page 412: ...tput Also LCD controller internal pins RS R W and STRB are input only pins and DB7 to DB0 input output is controlled by R W Therefore the following points must be noted 1 After reset release and stand...

Page 413: ...to 0 MOV B R0H PDR9 MOV B R0L PCR9 Output H 04 from port 9 MOV B R1H PDRA MOV B R1L PDRA Write H 04 to index register Read display data register MOV B R1L PCR9 Set port 9 to input mode MOV W H 0706 R...

Page 414: ...1 1 Common outputs COM1 to COM8 Segment outputs SEG1 to SEG40 Note COM9 to COM16 output common signal non selection waveforms 1 16 duty DDTY1 0 Common outputs COM1 to COM16 Segment outputs SEG1 to SEG...

Page 415: ...tion can be selected while the Y direction configuration is 16 bits Display data written from the CPU is stored horizontally with the MSB at the left and the LSB at the right as shown in figure 14 4 O...

Page 416: ...EG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 1 1 8 duty Display dots 320 Valid displ...

Page 417: ...side read See figure 14 6 for the procedure After the respective display data register LR4 accesses the X and Y addresses are automatically incremented on the basis of the value set in the INC bit in...

Page 418: ...Y address Y address 2 Priority given to X direction data access INC 1 1 2 3 Address register LR2 bits XA2 to XA0 show the X address and bits YA3 to YA0 show the Y address X address operation Address...

Page 419: ...t to accesses by the CPU However since simultaneous accesses would corrupt data in the RAM arbitration is carried out within the chip Basically accesses by the CPU have priority and reads for display...

Page 420: ...rite accesses to the display memory In read modify write mode the address is incremented only after a write and remains the same after a read By using this mode it is possible to read previously writt...

Page 421: ...odule standby state Figure 14 9 shows the procedures for initiating and clearing module standby mode The initiation and clearing procedures must be followed exactly in order to protect the display mem...

Page 422: ...Power Off Procedures 14 3 9 Power Supply Circuit The LCD controller has a built in bleeder resistance circuit for LCD drive In standby mode the voltage circuits are automatically turned off and the p...

Page 423: ...tances by setting the LPS1 bit to 1 in control register 2 LR1 Apply a voltage not exceeding VCC to pin V1OUT In either case inputting a voltage exceeding VCC may adversely affect the reliability of th...

Page 424: ...page 398 of 532 REJ09B0397 0300 V1 V2 V3 V4 V5 VSS V1 V2 V3 V4 V5 VSS V1 V2 V3 V4 V5 VSS V1 V2 V3 V4 V5 VSS V1 V2 V3 V4 V5 VSS COM1 COM2 COM16 1 frame Line selection period Not selected Selected SEG1...

Page 425: ...internal power supply is used and the built in bleeder resistances are employed bits LPS1 and LPS0 in control register 2 LR1 should both be set to 1 If the capacitance of the LCD panel to be driven is...

Page 426: ...3 The power supply applied to V1OUT must not exceed VCC If the capacitance of the LCD panel to be driven is large capacitors of around 0 1 to 0 5 F should be inserted between V1OUT to V5OUT and VSS to...

Page 427: ...he LPS1 and LPS0 bits in control register 2 LR1 to 0 and make the connections shown in figure 14 14 V1OUT V2OUT V3OUT V4OUT V5OUT VCC OFF OFF OFF OFF OFF OFF Rx Rx Rx Rx Rx V1 V2 V3 V4 V5 LPS1 0 LPS0...

Page 428: ...value lower than the optimum contrast will deteriorate but the LCD drive voltage the potential difference between V1 and VSS can be kept low If the output voltage falls and the LCD display becomes fai...

Page 429: ...to AVCC 0 3 V LCD power supply Vin 0 3 to VLCD 0 3 V 3 Operating temperature Topr 20 to 75 C 4 Storage temperature Tstg 55 to 125 C Caution Permanent damage may occur to the chip if maximum ratings ar...

Page 430: ...cations 15 2 1 Power Supply Voltage and Operating Range The power supply voltage and operating range of the H8 3855 H8 3856 and H8 3857 are indicated by the shaded region in the figures below 1 Power...

Page 431: ...00 0 312 5 62 5 3 0 VCC V Active mode medium speed kHz 4 0 5 5 16 384 19 200 8 192 9 600 4 096 4 800 3 0 VCC V Subactive mode Subsleep mode except CPU Watch mode except CPU SUB kHz 4 0 5 5 Note In cas...

Page 432: ...IH RES WKP0 to WKP7 IRQ0 to IRQ4 TMIB TMIC TMIF TEST2 FWE SCK1 SCK3 ADTRG VCC 4 0 V to 5 5 V 0 8 VCC 0 9 VCC VCC 0 3 VCC 0 3 V UD SI1 RXD VCC 4 0 V to 5 5 V 0 7 VCC VCC 0 3 V 0 8 VCC VCC 0 3 OSC1 VCC...

Page 433: ...P50 to P57 VCC 4 0 V to 5 5 V IOL 1 6 mA IOL 0 4 mA 0 6 0 5 V P20 to P27 P30 to P37 VCC 4 0 V to 5 5 V IOL 10 mA 1 5 V VCC 4 0 V to 5 5 V IOL 1 6 mA 0 6 IOL 0 4 mA 0 5 Input output leakage current II...

Page 434: ...5 A 1 2 Reference values VCC 3 3 V LCD not used 32 kHz crystal oscillator used SUB W 2 20 A 1 2 Reference values Subsleep mode current dissipation ISUBSP VCC VCC 3 3 V LCD on with 2X step up 32 kHz cr...

Page 435: ...CD VCC System clock oscillator Crystal Subclock oscillator Crystal Subsleep mode Only timer operates CPU stops VCC VLCD 6 0 V Watch mode Only time base clock operates CPU stops VCC VLCD 6 0 V When LCD...

Page 436: ...n IOL Output pins except in ports 2 and 3 Ports 2 and 3 All output pins VCC 4 0 V to 5 5 V VCC 4 0 V to 5 5 V 2 0 10 0 0 5 mA 1 Allowable output low current total IOL Output pins except in ports 2 and...

Page 437: ...0 2 0 10 0 5 0 MHz OSC clock OSC cycle time tOSC OSC1 OSC2 VCC 4 0 V to 5 5 V 100 0 200 0 1000 0 1000 0 ns 1 Figure 15 1 System clock cycle time tcyc 2 16 2000 0 tOSC ns 1 Subclock oscillation freque...

Page 438: ...100 0 ns Figure 15 2 RES pin low width tREL RES 10 tcyc Figure 15 3 Input pin high width tIH IRQ0 to IRQ4 WKP0 to WKP7 ADTRG TMIB TMIC TMIF 2 tcyc tsubcyc Figure 15 4 Input pin low width tIL IRQ0 to I...

Page 439: ...lock high width tSCKH SCK1 0 4 tScyc Figure 15 6 Input serial clock low width tSCKL SCK1 0 4 tScyc Figure 15 6 Input serial clock rise time tSCKr SCK1 VCC 4 0 V to 5 5 V 60 0 80 0 ns Figure 15 6 Input...

Page 440: ...n Typ Max Unit Figure Input clock cycle Asynchronous Synchronous tScyc 4 6 tcyc Figure 15 7 Input clock pulse width tSCKW 0 4 0 6 tScyc Figure 15 7 Transmit data delay time tTXD VCC 4 0 V to 5 5 V 1 t...

Page 441: ...7 AVSS 0 3 AVCC 0 3 V Analog power supply AIOPE AVCC AVCC 5 0 V 1 5 mA current AISTOP1 AVCC AVCC 5 0 V 300 A 2 Reference value AISTOP2 AVCC 5 0 A 3 Analog input capacitance CAIN AN0 to AN7 30 0 pF All...

Page 442: ...d 0 05 mA VLCD 4 V 6 20 k 1 LCD power supply current IEE VLCD VLCD 5 5 V fx 32 768 kHz 20 40 A 2 LCD power supply voltage VLCD VLCD VCC 7 0 V 3 Notes 1 Applies to the resistance RCOM between the V1OUT...

Page 443: ...LOUT VCC Vci 3 0 V IO 0 03 mA C 1 F X1 32 kHz Ta 25 C 5 96 V Figure 15 9 Reference values 3X step up output voltage VUP3 VLOUT VCC 3 0 V Vci 2 0 V IO 0 03 mA C 1 F X1 32 kHz Ta 25 C 5 90 V Figure 15 9...

Page 444: ...Wait time after PV bit clearing 1 4 s Maximum number of writes 1 4 N 1000 Times Erasing Wait time after SWE bit setting 1 x 10 s Wait time after ESU bit setting 1 y 200 s Wait time after E bit setting...

Page 445: ...agrams tOSC tCPL OSC1 tCPH VIH tCPr tCPf VIL Figure 15 1 System Clock Input Timing tXL X1 tXH VIH tXr tXf VIL Figure 15 2 Subclock Input Timing tREL RES VIL Figure 15 3 RES Pin Low Width Timing tIL IR...

Page 446: ...SCKL VIH or VOH VIL or VOL SCK1 SO1 tScyc tSCKH tSCKr tSCKf tSOD tSIS tSIH SI1 Note Output timing reference levels Load conditions are shown in figure 15 10 Output high Output low VOH 2 0 V VOL 0 8 V...

Page 447: ...levels Load conditions are shown in figure 15 10 Output high Output low VOH 2 0 V VOL 0 8 V VIH or VOH VIL or VOL VOH VOL Figure 15 8 SCI3 Input Output Timing in Synchronous Mode 1 F 1 F IO 3 0 V 2X s...

Page 448: ...e electrical specifications listed in this manual there may be differences in the actual values of the electrical characteristics operating margins noise margins and so forth due to differences in the...

Page 449: ...0 3 V 2 Operating temperature Topr 20 to 75 C 3 Storage temperature Tstg 55 to 125 C Caution Permanent damage may occur to the chip if maximum ratings are exceeded Normal operation should be under th...

Page 450: ...age and Operating Range The power supply voltage and operating range of the H8 3852 H8 3853 and H8 3854 are indicated by the shaded region in the figures below 1 Power Supply Voltage vs Oscillator Fre...

Page 451: ...ed kHz 4 0 5 5 16 384 19 200 8 192 9 600 4 096 4 800 3 0 2 7 2 VCC V Subactive mode Subsleep mode except CPU Watch mode except CPU SUB kHz 4 0 5 5 1 1 1 Notes 1 In case of external clock only 2 The mi...

Page 452: ...able Pins Test Conditions Min Typ Max Unit Notes Input high voltage VIH RES WKP0 to WKP7 IRQ0 IRQ1 IRQ3 IRQ4 TMIB TMIF TEST2 FWE SCK3 ADTRG VCC 4 0 V to 5 5 V 0 8 VCC 0 9 VCC VCC 0 3 VCC 0 3 V RXD VCC...

Page 453: ...V to 5 5 V IOH 0 5 mA IOH 0 1 mA VCC 1 0 VCC 0 5 VCC 0 5 V Output low voltage VOL P10 to P12 P15 P17 P40 to P42 P50 to P57 VCC 4 0 V to 5 5 V IOL 1 6 mA IOL 0 4 mA 0 6 0 5 V P20 to P27 VCC 4 0 V to 5...

Page 454: ...C 10 MHz A D not used 4 3 7 0 mA 1 2 Subactive mode current dissipation ISUB VCC VCC 5 0 V LCD on 32 kHz crystal oscillator used SUB W 2 80 160 A 1 2 5 VCC 5 0 V LCD on 32 kHz crystal oscillator used...

Page 455: ...p mode Only timer operates VCC Subactive mode Operates VCC System clock oscillator Crystal Subclock oscillator Crystal Subsleep mode Only timer operates CPU stops VCC Watch mode Only time base clock o...

Page 456: ...it Notes Allowable output low current per pin IOL Output pins except in port 2 Port 2 All output pins VCC 4 0 V to 5 5 V VCC 4 0 V to 5 5 V 2 0 10 0 0 5 mA 1 Allowable output low current total IOL Out...

Page 457: ...OSC2 VCC 4 0 V to 5 5 V 2 0 2 0 10 0 5 0 MHz OSC clock OSC cycle time tOSC OSC1 OSC2 VCC 4 0 V to 5 5 V 100 0 200 0 1000 0 1000 0 ns 1 Figure 16 1 System clock cycle time tcyc 2 16 2000 0 tOSC ns 1 S...

Page 458: ...xternal subclock fall time tXf X1 100 0 ns Figure 16 2 RES pin low width tREL RES 10 tcyc Figure 16 3 Input pin high width tIH IRQ0 IRQ1 IRQ3 IRQ4 WKP0 to WKP7 ADTRG TMIB TMIF 2 tcyc tsubcyc Figure 16...

Page 459: ...Item Symbol Test Conditions Min Typ Max Unit Figure Input clock cycle Asynchronous Synchronous tScyc 4 6 tcyc Figure 16 5 Input clock pulse width tSCKW 0 4 0 6 tScyc Figure 16 5 Transmit data delay t...

Page 460: ...H8 3854 VCC 3 0 V to 5 5 V of H8 3854F VSS 0 0 V Ta 20 C to 75 C unless otherwise specified Applicable Test Values Reference Item Symbol Pins Conditions Min Typ Max Unit Figure Analog input voltage A...

Page 461: ...st Conditions Min Typ Max Unit Notes Common driver on resistance RCOM COM1 to COM16 Id 0 05 mA VCC 4 V 6 20 k 1 Segment driver on resistance RSEG SEG1 to SEG40 Id 0 05 mA VCC 4 V 6 20 k 1 LCD power su...

Page 462: ...er PV bit clearing 1 4 s Maximum number of writes 1 4 N 1000 Times Erasing Wait time after SWE bit setting 1 x 10 s Wait time after ESU bit setting 1 y 200 s Wait time after E bit setting 1 5 z 5 ms W...

Page 463: ...timing diagrams tOSC tCPL OSC1 tCPH VIH tCPr tCPf VIL Figure 16 1 System Clock Input Timing tXL X1 tXH VIH tXr tXf VIL Figure 16 2 Subclock Input Timing tREL RES VIL Figure 16 3 RES Pin Low Width Timi...

Page 464: ...ata tTXD tScyc tRXH tRXS Note Output timing reference levels Load conditions are shown in figure 16 7 Output high Output low VOH 2 0 V VOL 0 8 V VIH or VOH VIL or VOL VOH VOL Figure 16 6 SCK3 Input Ou...

Page 465: ...here may be differences in the actual values of the electrical characteristics operating margins noise margins and so forth due to differences in the fabrication process the on chip ROM and the layout...

Page 466: ...16 Electrical Characteristics H8 3854 Group Rev 3 00 Jul 19 2007 page 440 of 532 REJ09B0397 0300...

Page 467: ...er source 8 or 16 bits Rn8 16 General register 8 or 16 bits CCR Condition code register N N negative flag in CCR Z Z zero flag in CCR V V overflow flag in CCR C C carry flag in CCR PC Program counter...

Page 468: ...00 Jul 19 2007 page 442 of 532 REJ09B0397 0300 Condition Code Notation Symbol Description Modified according to the instruction result Not fixed value not guaranteed 0 Always cleared to 0 Not affected...

Page 469: ...Rs16 2 0 6 MOV B aa 8 Rd B aa 8 Rd8 2 0 4 MOV B aa 16 Rd B aa 16 Rd8 4 0 6 MOV B Rs Rd B Rs8 Rd16 2 0 4 MOV B Rs d 16 Rd B Rs8 d 16 Rd16 4 0 6 MOV B Rs Rd B Rd16 1 Rd16 Rs8 Rd16 2 0 6 MOV B Rs aa 8 B...

Page 470: ...8 Rd B Rd8 xx 8 C Rd8 2 2 2 ADDX B Rs Rd B Rd8 Rs8 C Rd8 2 2 2 ADDS W 1 Rd W Rd16 1 Rd16 2 2 ADDS W 2 Rd W Rd16 2 Rd16 2 2 INC B Rd B Rd8 1 Rd8 2 2 DAA B Rd B Rd8 decimal adjust Rd8 2 3 2 SUB B Rs Rd...

Page 471: ...d16 RdH remainder RdL quotient 2 5 6 14 AND B xx 8 Rd B Rd8 xx 8 Rd8 2 0 2 AND B Rs Rd B Rd8 Rs8 Rd8 2 0 2 OR B xx 8 Rd B Rd8 xx 8 Rd8 2 0 2 OR B Rs Rd B Rd8 Rs8 Rd8 2 0 2 XOR B xx 8 Rd B Rd8 xx 8 Rd8...

Page 472: ...LR xx 3 Rd B xx 3 of Rd8 0 2 2 BCLR xx 3 Rd B xx 3 of Rd16 0 4 8 BCLR xx 3 aa 8 B xx 3 of aa 8 0 4 8 BCLR Rn Rd B Rn8 of Rd8 0 2 2 BCLR Rn Rd B Rn8 of Rd16 0 4 8 BCLR Rn aa 8 B Rn8 of aa 8 0 4 8 BNOT...

Page 473: ...BST xx 3 aa 8 B C xx 3 of aa 8 4 8 BIST xx 3 Rd B C xx 3 of Rd8 2 2 BIST xx 3 Rd B C xx 3 of Rd16 4 8 BIST xx 3 aa 8 B C xx 3 of aa 8 4 8 BAND xx 3 Rd B C xx 3 of Rd8 C 2 2 BAND xx 3 Rd B C xx 3 of Rd...

Page 474: ...a 8 C 4 6 BRA d 8 BT d 8 PC PC d 8 2 4 BRN d 8 BF d 8 PC PC 2 2 4 BHI d 8 If C Z 0 2 4 BLS d 8 condition C Z 1 2 4 BCC d 8 BHS d 8 is true C 0 2 4 BCS d 8 BLO d 8 then C 1 2 4 BNE d 8 PC Z 0 2 4 BEQ d...

Page 475: ...xx 8 CCR B CCR xx 8 CCR 2 2 ORC xx 8 CCR B CCR xx 8 CCR 2 2 XORC xx 8 CCR B CCR xx 8 CCR 2 2 NOP PC PC 2 2 2 EEPMOV if R4L 0 Repeat R5 R6 R5 1 R5 R6 1 R6 R4L 1 R4L Until R4L 0 else next 4 4 Notes 1 Se...

Page 476: ...Table A 2 is an operation code map It shows the operation codes contained in the first byte of the instruction code bits 15 to 8 of the first instruction word Instruction when first bit of byte 2 bit...

Page 477: ...SHLR SHAR STC BHI BCLR ROTXL ROTL LDC BLS BTST ROTXR ROTR ORC OR BCC RTS XORC XOR BCS BSR BOR BIOR BXOR BIXOR BAND BIAND ANDC AND BNE RTE LDC BEQ NOT NEG BLD BILD BST BIST ADD SUB BVC BVS MOV INC DEC...

Page 478: ...ruction The total number of states required for execution of an instruction can be calculated from these two tables as follows Execution states I SI J SJ K SK L SL M SM N SN Examples When instruction...

Page 479: ...n Execution Status Access Location Instruction Cycle On Chip Memory On Chip Peripheral Module Instruction fetch SI 2 Branch address read SJ Stack operation SK Byte data access SL 2 or 3 Word data acce...

Page 480: ...8 Rd 1 ADD B Rs Rd 1 ADD W Rs Rd 1 ADDS ADDS W 1 Rd 1 ADDS W 2 Rd 1 ADDX ADDX B xx 8 Rd 1 ADDX B Rs Rd 1 AND AND B xx 8 Rd 1 AND B Rs Rd 1 ANDC ANDC xx 8 CCR 1 BAND BAND xx 3 Rd 1 BAND xx 3 Rd 2 1 BA...

Page 481: ...BILD BILD xx 3 Rd 1 BILD xx 3 Rd 2 1 BILD xx 3 aa 8 2 1 BIOR BIOR xx 3 Rd 1 BIOR xx 3 Rd 2 1 BIOR xx 3 aa 8 2 1 BIST BIST xx 3 Rd 1 BIST xx 3 Rd 2 2 BIST xx 3 aa 8 2 2 BIXOR BIXOR xx 3 Rd 1 BIXOR xx...

Page 482: ...xx 3 Rd 2 1 BTST xx 3 aa 8 2 1 BTST Rn Rd 1 BTST Rn Rd 2 1 BTST Rn aa 8 2 1 BXOR BXOR xx 3 Rd 1 BXOR xx 3 Rd 2 1 BXOR xx 3 aa 8 2 1 CMP CMP B xx 8 Rd 1 CMP B Rs Rd 1 CMP W Rs Rd 1 DAA DAA B Rd 1 DAS...

Page 483: ...Rs Rd 1 1 2 MOV B aa 8 Rd 1 1 MOV B aa 16 Rd 2 1 MOV B Rs Rd 1 1 MOV B Rs d 16 Rd 2 1 MOV B Rs Rd 1 1 2 MOV B Rs aa 8 1 1 MOV B Rs aa 16 2 1 MOV W xx 16 Rd 2 MOV W Rs Rd 1 MOV W Rs Rd 1 1 MOV W d 16 R...

Page 484: ...a Access M Internal Operation N ROTXL ROTXL B Rd 1 ROTXR ROTXR B Rd 1 RTE RTE 2 2 2 RTS RTS 2 1 2 SHAL SHAL B Rd 1 SHAR SHAR B Rd 1 SHLL SHLL B Rd 1 SHLR SHLR B Rd 1 SLEEP SLEEP 1 STC STC CCR Rd 1 SUB...

Page 485: ...it 4 Bit 3 Bit 2 Bit 1 Bit 0 Name H 80 FLMCR1 1 FWE SWE EV PV E P Flash H 81 FLMCR2 1 FLER ESU PSU memory H 82 H 83 EBR 1 EB6 EB5 EB4 EB3 EB2 EB1 EB0 H 84 H 85 H 86 H 87 H 88 H 89 MDCR 1 TSDS2 TSDS1 H...

Page 486: ...RE MPIE TEIE CKE1 CKE0 H AB TDR TDR7 TDR6 TDR5 TDR4 TDR3 TDR2 TDR1 TDR0 H AC SSR TDRE RDRF OER FER PER TEND MPBR MPBT H AD RDR RDR7 RDR6 RDR5 RDR4 RDR3 RDR2 RDR1 RDR0 H AE H AF H B0 TMA TMA7 TMA6 TMA5...

Page 487: ...ADRR ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 converter H C6 ADSR ADSF H C7 H C8 PMR1 IRQ3 IRQ2 IRQ1 PWM TMOFH TMOFL TMOW I O ports H C9 PMR2 IRQ0 POF1 UD IRQ4 H CA PMR3 SO1 SI1 SCK1 H CB PMR4 NMOD7 NM...

Page 488: ...CR15 PCR14 PCR13 PCR12 PCR11 PCR10 H E5 PCR2 PCR27 PCR26 PCR25 PCR24 PCR23 PCR22 PCR21 PCR20 H E6 PCR3 PCR37 PCR36 PCR35 PCR34 PCR33 PCR32 PCR31 PCR30 H E7 PCR4 PCR42 PCR41 PCR40 H E8 PCR5 PCR57 PCR56...

Page 489: ...munication interface 1 SCI3 Serial communication interface 3 Notes 1 Applies to the F ZTAT version In the mask ROM version a read access to the address of a register other than MDCR will always return...

Page 490: ...FLMCR1 1 FWE SWE EV PV E P Flash H 81 FLMCR2 1 FLER ESU PSU memory H 82 H 83 EBR 1 EB6 EB5 EB4 EB3 EB2 EB1 EB0 H 84 H 85 H 86 H 87 H 88 H 89 MDCR 1 TSDS2 TSDS1 H 8A H 8B H 8C H 8D H 8E H 8F SYSCR3 1...

Page 491: ...R5 RDR4 RDR3 RDR2 RDR1 RDR0 H AE H AF H B0 TMA TMA7 TMA6 TMA5 TMA3 TMA2 TMA1 TMA0 Timer A H B1 TCA TCA7 TCA6 TCA5 TCA4 TCA3 TCA2 TCA1 TCA0 H B2 TMB TMB7 TMB2 TMB1 TMB0 Timer B H B3 TCB TLB TCB7 TLB7 T...

Page 492: ...C9 PMR2 IRQ0 IRQ4 H CA H CB PMR4 NMOD7 NMOD6 NMOD5 NMOD4 NMOD3 NMOD2 NMOD1 NMOD0 H CC PMR5 WKP7 WKP6 WKP5 WKP4 WKP3 WKP2 WKP1 WKP0 H CD H CE H CF H D0 H D1 H D2 H D3 H D4 PDR1 P17 P15 P12 P11 P10 I O...

Page 493: ...CR2 NESEL DTON MSON SA1 SA0 control H F2 IEGR IEG4 IEG3 IEG1 IEG0 H F3 IENR1 IENTA IENWP IEN4 IEN3 IEN1 IEN0 H F4 IENR2 IENDT IENAD IENTFH IENTFL IENTB H F5 H F6 IRR1 IRRTA IRRI4 IRRI3 IRRI1 IRRI0 H F...

Page 494: ...Bit Initial value Read Write 7 TMC7 0 R W 6 TMC6 0 R W 5 TMC5 0 R W 3 1 0 TMC0 0 R W 2 TMC2 0 R W 1 TMC1 0 R W 4 1 Clock select 0 Internal clock Legend Don t care Internal clock 0 0 1 Internal clock I...

Page 495: ...mode Setting condition When FWE 1 SWE 1 and PSU 1 Erase Erase mode cleared Transition to erase mode Setting condition When FWE 1 SWE 1 and ESU 1 1 0 1 Program verify 0 Program verify mode cleared 1 T...

Page 496: ...lly Flash memory program erase protection error protection is disabled Clearing condition Reset or hardware standby mode An error occurred during flash memory programming erasing Flash memory program...

Page 497: ...6 EB6 0 R W 5 EB5 0 R W 4 EB4 0 R W 3 EB3 0 R W 0 EB0 0 R W 2 EB2 0 R W 1 EB1 0 R W Bit Initial value Read Write Block Size Flash memory erase blocks EB0 1 kbyte EB1 1 kbyte EB2 1 kbyte EB3 1 kbyte EB...

Page 498: ...2 0 1 TSDS2 R Bit Initial value Read Write Note Determined by the TEST and TEST2 pins Test pin monitor bits SYSCR3 System control register 3 H 8F Flash memory On chip flash memory version only 7 0 6...

Page 499: ...Writing to bit 2 is disabled Bit 2 write inhibit 0 1 Writing to bits 2 and 0 is disabled Writing to bits 2 and 0 is enabled Timer control status register W write enable 0 1 Writing to bit 4 is enabled...

Page 500: ...r W H 92 Flash memory On chip flash memory version only 7 1 6 1 5 1 4 1 3 1 2 1 R W 1 1 R W 0 CKS2 CKS1 CKS0 1 R W Description Clock select Bit 2 CKS2 0 0 0 0 1 1 1 1 Bit 1 CKS1 0 0 1 1 0 0 1 1 Bit 0...

Page 501: ...t 0 Clock source is prescaler S and pin SCK is output pin 1 Clock source is external clock and pin SCK is input pin 0 8 bit synchronous transfer mode 16 bit synchronous transfer mode 1 0 1 0 1 Continu...

Page 502: ...0 Indicates that transfer is stopped Invalid 1 Read Write Read Write Indicates transfer in progress Starts a transfer operation Note Only a write of 0 for flag clearing is possible 0 Clearing conditio...

Page 503: ...1 SDRU1 Undefined R W Used to set transmit data and store receive data 8 bit transfer mode 16 bit transfer mode Not used Upper 8 bits of data SDRL Serial data register L H A3 SCI1 H8 3857 Group only...

Page 504: ...enabled Clock select 0 1 0 0 1 1 0 1 clock 4 clock 16 clock 64 clock Multiprocessor mode 0 Multiprocessor communication function disabled 1 Multiprocessor communication function enabled Stop bit leng...

Page 505: ...Asynchronous Internal clock I O port Synchronous Internal clock Serial clock output 1 Asynchronous Internal clock Clock output Synchronous Reserved Do not set this combination Reserved Do not set this...

Page 506: ...Jul 19 2007 page 480 of 532 REJ09B0397 0300 TDR Transmit data register H AB SCI3 Bit Initial value Read Write 7 TDR7 1 R W 6 TDR6 1 R W 5 TDR5 1 R W 4 TDR4 1 R W 3 TDR3 1 R W 0 TDR0 1 R W 2 TDR2 1 R W...

Page 507: ...not match the parity mode bit PM setting in the serial mode register SMR 0 Indicates that data receiving is in progress or has been completed Framing error Clearing condition After reading FER 1 clear...

Page 508: ...e Read Write 7 TMA7 0 R W 6 TMA6 0 R W 5 TMA5 0 R W 0 TMA0 0 R W 2 TMA2 0 R W 1 TMA1 0 R W Internal clock select TMA3 TMA2 0 PSS PSS PSS PSS 0 4 1 Clock output select 0 32 16 TMA1 0 1 TMA0 0 0 1 1 PSS...

Page 509: ...e TMB Timer mode register B H B2 Timer B Bit Initial value Read Write 7 TMB7 0 R W 6 1 5 1 3 1 0 TMB0 0 R W 2 TMB2 0 R W 1 TMB1 0 R W 4 1 Auto reload function select Clock select 0 Internal clock Inte...

Page 510: ...B3 Timer B Bit Initial value Read Write 7 TCB7 0 R 6 TCB6 0 R 5 TCB5 0 R 4 TCB4 0 R 3 TCB3 0 R 0 TCB0 0 R 2 TCB2 0 R 1 TCB1 0 R Count value TLB Timer load register B H B3 Timer B Bit Initial value Rea...

Page 511: ...lock Internal clock Internal clock External event TMIC 8192 2048 512 64 16 4 4 Rising or falling edge 0 Interval timer function selected 1 Auto reload function selected W Counter up down control TCC i...

Page 512: ...ial value Read Write 7 TOLH 0 W 6 CKSH2 0 W 5 CKSH1 0 W 3 TOLL 0 W 0 CKSL0 0 W 2 CKSL2 0 W 1 CKSL1 0 W 4 CKSH0 0 W Toggle output level H Clock select L 0 1 0 0 1 1 0 1 Internal clock Internal clock In...

Page 513: ...H 0 Clearing condition After reading CMFH 1 cleared by writing 0 to CMFH 1 Setting condition When the TCFH value matches the OCRFH value 0 TCFH overflow interrupt disabled 1 TCFH overflow interrupt e...

Page 514: ...l value Read Write 7 TCFL7 0 R W 6 TCFL6 0 R W 5 TCFL5 0 R W 4 TCFL4 0 R W 3 TCFL3 0 R W 0 TCFL0 0 R W 2 TCFL2 0 R W 1 TCFL1 0 R W Count value OCRFH Output compare register FH H BA Timer F Bit Initial...

Page 515: ...rigger select 0 Disables start of A D conversion by external trigger 1 Enables start of A D conversion by rising or falling edge of external trigger at pin ADTRG 5 1 4 AN5 AN6 AN7 Reserved 1 0 0 1 1 0...

Page 516: ...ndefined R 4 ADR4 Undefined R 3 ADR3 Undefined R 0 ADR0 Undefined R 2 ADR2 Undefined R 1 ADR1 Undefined R A D conversion result ADSR A D start register H C6 A D converter Bit Initial value Read Write...

Page 517: ...P1 TMOFH pin function switch 0 Functions as P1 I O pin 1 Functions as TMOFH input pin P1 PWM pin function switch 0 Functions as P1 I O pin 1 Functions as PWM output pin P1 IRQ TMIB pin function switc...

Page 518: ...0 Functions as P2 I O pin 1 Functions as UD input pin P3 SO pin PMOS control 0 CMOS output 1 NMOS open drain output P2 IRQ ADTRG pin function switch 1 0 Functions as P2 I O pin 1 Functions as IRQ ADT...

Page 519: ...ons as P3 I O pin 1 Functions as SCK I O pin P3 SI pin function switch 0 Functions as P3 I O pin 1 Functions as SI input pin P3 SO pin function switch 0 Functions as P3 I O pin 1 Functions as SO outpu...

Page 520: ...ister H D0 14 bit PWM H8 3857 Group only Bit Initial value Read Write 7 1 6 1 5 1 4 1 3 1 0 PWCR0 0 W 2 1 1 1 Clock select 0 The input clock is 2 t 2 The conversion period is 16 384 with a minimum mod...

Page 521: ...e 7 P17 0 R W 6 P16 0 R W 5 P15 0 R W 4 P14 0 R W 3 P13 0 R W 0 P10 0 R W 2 P12 0 R W 1 P11 0 R W Note P16 P14 and P13 are functions of the H8 3857 Group only In the H8 3854 Group these bits are reser...

Page 522: ...2 P5 0 R W 1 P5 0 R W 3 0 2 1 4 5 6 7 PDR9 Port data register 9 H DC I O ports Bit Initial value Read Write 7 P9 0 R W 6 P9 0 R W 5 P9 0 R W 4 P9 0 R W 3 P9 0 R W 0 P9 0 R W 2 P9 0 R W 1 P9 0 R W 3 0...

Page 523: ...value Read Write 7 PUCR3 0 R W 6 PUCR3 0 R W 5 PUCR3 0 R W 4 PUCR3 0 R W 3 PUCR3 0 R W 0 PUCR3 0 R W 2 PUCR3 0 R W 1 PUCR3 0 R W 3 0 2 1 4 5 6 7 PUCR5 Port pull up control register 5 H E2 I O ports Bi...

Page 524: ...0 Input pin 1 Output pin 7 6 5 4 3 0 2 1 PCR3 Port control register 3 H E6 I O ports H8 3857 Group only Bit Initial value Read Write 7 PCR3 0 W 6 PCR3 0 W 5 PCR3 0 W 4 PCR3 0 W 3 PCR3 0 W 0 PCR3 0 W...

Page 525: ...elect 0 Input pin 1 Output pin 7 6 5 4 3 0 2 1 PCR9 Port control register 9 H EC I O ports Bit Initial value Read Write 7 PCR9 0 W 6 PCR9 0 W 5 PCR9 0 W 4 PCR9 0 W 3 PCR9 0 W 0 PCR9 0 W 2 PCR9 0 W 1 P...

Page 526: ...by timer select 2 to 0 0 Wait time 8 192 states Wait time 16 384 states 0 0 1 Wait time 32 768 states Wait time 65 536 states 1 0 1 1 Wait time 131 072 states Low speed on flag 0 The CPU operates on t...

Page 527: ...is made to active medium speed mode if SSBY 0 MSON 1 and LSON 0 or to subactive mode if SSBY 1 TMA3 1 and LSON 1 Subactive mode clock select 0 8 4 0 1 1 2 W W W Noise elimination sampling frequency se...

Page 528: ...edge of IRQ TMIB pin input is detected 1 Rising edge of IRQ TMIB pin input is detected 1 1 1 IRQ edge select 0 Falling edge of IRQ TMIC pin input is detected 1 Rising edge of IRQ TMIC pin input is de...

Page 529: ...0 Disables interrupt request IRQ 1 4 n 0 Enables interrupt request IRQ n Wakeup interrupt enable 0 Disables interrupt requests from WKP to WKP 1 7 0 Enables interrupt requests from WKP to WKP 7 0 SCI1...

Page 530: ...timer FH interrupts 1 Enables timer FH interrupts Timer C interrupt enable 0 Disables timer C interrupts 1 Enables timer C interrupts Timer FL interrupt enable 0 Disables timer FL interrupts 1 Enable...

Page 531: ...ring condition When IRRS1 1 it is cleared by writing 0 1 Setting condition When an SCI1 transfer is completed IRQ to IRQ interrupt request flag 0 Clearing conditions When IRRI4 1 it is cleared by writ...

Page 532: ...When IRRTFH 1 it is cleared by writing 0 When counter FH matches output compare register FH in 8 bit mode or when 16 bit counter F TCFL TCFH matches 16 bit output compare register F OCRFL OCRFH in 16...

Page 533: ...te 7 IWPF7 0 R W 6 IWPF6 0 R W 5 IWPF5 0 R W 4 IWPF4 0 R W 3 IWPF3 0 R W 0 IWPF0 0 R W 2 IWPF2 0 R W 1 IWPF1 0 R W Note Only a write of 0 for flag clearing is possible Wakeup interrupt request flag 0...

Page 534: ...MR1 PUCR1 Port data register 1 Port control register 1 Port mode register 1 Port pull up control register 1 VCC VCC IRQ TMIB P15 TMIC P16 Timer B module Timer C module Timer F module TMIF P17 n 4 VSS...

Page 535: ...0300 SBY PUCR14 PMR14 PDR14 PCR14 Internal data bus PWM Legend PDR1 PCR1 PMR1 PUCR1 Port data register 1 Port control register 1 Port mode register 1 Port pull up control register 1 VCC PWM module P1...

Page 536: ...e 510 of 532 REJ09B0397 0300 SBY PUCR13 PDR13 PCR13 Internal data bus Legend PDR1 PCR1 PUCR1 Port data register 1 Port control register 1 Port pull up control register 1 P13 VCC VCC VSS Figure C 1 c P...

Page 537: ...UCR1n PMR1n PDR1n PCR1n Internal data bus TMOFH P1 TMOFL P1 Legend PDR1 PCR1 PMR1 PUCR1 Note n 2 or 1 Port data register 1 Port control register 1 Port mode register 1 Port pull up control register 1...

Page 538: ...32 REJ09B0397 0300 PUCR10 PMR10 PDR10 PCR10 Internal data bus TMOW Legend PDR1 PCR1 PMR1 PUCR1 Port data register 1 Port control register 1 Port mode register 1 Port pull up control register 1 Timer A...

Page 539: ...gram of Port 2 PMR4n PDR2n PCR2n Internal data bus Legend PDR2 PCR2 PMR4 Notes H8 3857 Group n 7 to 2 H8 3854 Group n 7 to 1 Port data register 2 Port control register 2 Port mode register 4 P2n VCC V...

Page 540: ...532 REJ09B0397 0300 PMR41 PMR21 PDR21 PCR21 Internal data bus Legend PDR2 PCR2 PMR2 PMR4 Port data register 2 Port control register 2 Port mode register 2 Port mode register 4 UD Timer C module P21 V...

Page 541: ...532 REJ09B0397 0300 PMR40 PMR20 PDR20 PCR20 Internal data bus Legend PDR2 PCR2 PMR2 PMR4 Port data register 2 Port control register 2 Port mode register 2 Port mode register 4 IRQ4 P20 VCC VSS SBY A...

Page 542: ...ock Diagram of Port 3 H8 3857 Group Only P3n VCC VCC PUCR3n Internal data bus PDR3n PCR3n SBY VSS Legend PDR3 PCR3 PUCR3 Note n 7 to 3 Port data register 3 Port control register 3 Port pull up control...

Page 543: ...2 PMR32 PDR32 PCR32 Internal data bus SO1 Legend PDR3 PCR3 PMR3 PMR2 PUCR3 Port data register 3 Port control register 3 Port mode register 3 Port mode register 2 Port pull up control register 3 SCI1 m...

Page 544: ...0300 P31 VCC VCC PUCR31 Internal data bus PMR31 PDR31 PCR31 SBY VSS SCI1 module Legend PDR3 PCR3 PMR3 PUCR3 Port data register 3 Port control register 3 Port mode register 3 Port pull up control regis...

Page 545: ...P30 VCC VCC PUCR30 Internal data bus SCI1 module PMR30 PDR30 PCR30 SBY VSS EXCK SCKO SCKI Legend PDR3 PCR3 PMR3 PUCR3 Port data register 3 Port control register 3 Port mode register 3 Port pull up con...

Page 546: ...k Diagram of Port 4 PMR23 Internal data bus Legend PMR2 Port mode register 2 IRQ0 P43 Figure C 4 a Port 4 Block Diagram Pin P43 PDR42 PCR42 Internal data bus TE TXD Legend PDR4 PCR4 Port data register...

Page 547: ...agrams Rev 3 00 Jul 19 2007 page 521 of 532 REJ09B0397 0300 PDR41 PCR41 Legend PDR4 PCR4 Port data register 4 Port control register 4 RE RXD SCI3 module P41 VCC VSS Internal data bus SBY Figure C 4 c...

Page 548: ...ev 3 00 Jul 19 2007 page 522 of 532 REJ09B0397 0300 PDR40 PCR40 SCKIE SCKOE SCKO SCKI Legend PDR4 PCR4 Port data register 4 Port control register 4 SCI3 module P40 VCC VSS Internal data bus SBY Figure...

Page 549: ...0397 0300 C 5 Block Diagram of Port 5 PUCR5n PMR5n PDR5n PCR5n Internal data bus Legend PDR5 PCR5 PMR5 PUCR5 Note n 7 to 0 Port data register 5 Port control register 5 Port mode register 5 Port pull u...

Page 550: ...Rev 3 00 Jul 19 2007 page 524 of 532 REJ09B0397 0300 C 6 Block Diagram of Port 9 PDR9n PCR9n Internal data bus Legend PDR9 PCR9 Note n 7 to 0 Port data register 9 Port control register 9 P9n VCC VSS S...

Page 551: ...Rev 3 00 Jul 19 2007 page 525 of 532 REJ09B0397 0300 C 7 Block Diagram of Port A PDRAn PCRAn Internal data bus Legend PDRA PCRA Note n 3 to 0 Port data register A Port control register A PAn VCC VSS S...

Page 552: ...age 526 of 532 REJ09B0397 0300 C 8 Block Diagram of Port B DEC Internal data bus AMR0 to AMR3 V A D module IN PBn Notes H8 3857 Group n 7 to 0 H8 3854 Group n 7 to 4 Figure C 8 Port B Block Diagram Pi...

Page 553: ...pedance 2 Retained Functions Functions P43 to P40 High impedance Retained Retained High impedance Retained Functions Functions P57 to P50 High impedance Retained Retained High impedance 2 Retained Fun...

Page 554: ...ROM Standard HD6433855FQ HD6433855 FQ 144 pin QFP FP 144H versions models HD6433855TG HD6433855 TG 144 pin TQFP TFP 144 HCD6433855 Die Table E 2 H8 3854 Group Product Code Lineup Product Type Part No...

Page 555: ...D E A2 HD A bp b1 c x y ZD ZE L1 Max Nom Min Dimension in Millimeters Symbol Reference 1 25 20 21 7 22 0 22 3 0 08 0 6 0 5 0 4 0 15 0 20 20 1 45 22 3 22 0 21 7 1 70 0 20 0 12 0 04 0 27 0 22 0 17 0 22...

Page 556: ...17 8 18 0 18 2 1 00 16 0 16 0 15 0 4 0 5 0 6 0 07 18 2 18 0 17 8 Reference Symbol Dimension in Millimeters Min Nom Max L1 ZE ZD y x c b1 bp A HD A2 E D A1 c1 e e L HE Index mark 1 2 3 73 72 108 109 3...

Page 557: ...cross section p 1 1 c b c b 2 1 1 Detail F c A A L L A 1 0 1 0 0 08 0 10 0 5 8 0 0 25 0 12 0 15 0 20 0 00 0 27 0 22 0 17 0 22 0 17 0 12 3 05 16 3 16 0 15 7 L1 ZE ZD y x c b1 bp A HD A2 E D A1 c1 e e...

Page 558: ...Detail F c A A L A L Terminal cross section 1 1 p b c c b HE L e e c1 A1 D E A2 HD A bp b1 c x y ZD ZE L1 Reference Symbol Dimension in Millimeters Min Nom Max 1 0 0 10 0 8 0 4 0 12 0 17 0 22 0 13 0...

Page 559: ...3854 F ZTAT Publication Date 1st Edition March 1999 Rev 3 00 July 19 2007 Published by Sales Strategic Planning Div Renesas Technology Corp Edited by Customer Support Department Global Strategic Commu...

Page 560: ...Renesas Technology Hong Kong Ltd 7th Floor North Tower World Finance Centre Harbour City 1 Canton Road Tsimshatsui Kowloon Hong Kong Tel 852 2265 6688 Fax 852 2730 6071 Renesas Technology Taiwan Co L...

Page 561: ......

Page 562: ...1753 Shimonumabe Nakahara ku Kawasaki shi Kanagawa 211 8668 Japan H8 3857 Group H8 3857 F ZTAT H8 3854 Group H8 3854 F ZTAT REJ09B0397 0300 Hardware Manual...

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