Renesas F-ZTAT H8 Series, Hardware Manual

Page: 290 / 562

10. Serial Communication Interface
Rev.3.00 Jul. 19, 2007 page 264 of 532
REJ09B0397-0300
TSR cannot be read or written directly by the CPU.
Transmit Data Register (TDR)
Bit 7 6 5 4 3 2 1 0
TDR7 TDR6 TDR5 TDR4 TDR3 TDR2 TDR1 TDR0
Initial value 1 1 1 1 1 1 1 1
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
The transmit data register (TDR) is an 8-bit register for holding transmit data.
When SCI3 detects that the transmit shift register (TSR) is empty, it shifts transmit data written in
TDR to TSR and starts serial data transmission. While TSR is transmitting serial data, the next
byte to be transmitted can be written to TDR, realizing continuous transmission.
TDR can be read or written by the CPU at all times.
TDR is initialized to H'FF upon reset or in standby mode, watch mode, subactive mode, or
subsleep mode.
Serial Mode Register (SMR)
Bit 7 6 5 4 3 2 1 0
COM CHR PE PM STOP MP CKS1 CKS0
Initial value 0 0 0 0 0 0 0 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
The serial mode register (SMR) is an 8-bit register for setting the serial data communication
format and for selecting the clock source of the baud rate generator. SMR can be read and written
by the CPU at any time.
SMR is initialized to H'00 upon reset or in standby mode, watch mode, subactive mode, or
subsleep mode.
Bit 7—Communication Mode (COM): Bit 7 selects asynchronous mode or synchronous mode
as the serial data communication mode.
Bit 7: COM Description
0 Asynchronous mode (initial value)
1 Synchronous mode