6. ROM
Rev.3.00 Jul. 19, 2007 page 121 of 532
REJ09B0397-0300
6.2.2 Block
Diagram
Bus interface/controller
Operating
mode
FLMCR1
SYSCR3
SYSCR3
FLMCR1
FLMCR2
EBR
: System control register 3
*
: Flash memory control register 1
*
: Flash memory control register 2
*
: Erase block register
*
Legend:
Note:
*
Internal data bus (lower 8 bits)
Internal data bus (upper 8 bits)
FWE pin
TEST2 pin
TEST pin
FLMCR2
EBR
MDCR
H'0000
H'0002
H'0004
H'EDFC
H'EDFE
Upper byte
(even address)
Lower byte
(odd address)
H'0001
H'0003
H'0005
H'EDFD
H'EDFF
On-chip flash memory (60 kbytes)
The registers that control the flash memory (FLMCR1, FLMCR2, EBR, and MDCR)
are for use exclusively by the flash memory version, and are not provided in the
mask ROM version.
In the mask ROM version, a read access to the address of a register other than
MDCR will always return 0, a read access to the address (H'FF89) corresponding to
MDCR will return an undefined value, and writes are invalid.
Figure 6.2 Block Diagram of Flash Memory
Summary of Contents for F-ZTAT H8 Series
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