Appendix B Internal I/O Registers
Rev.3.00 Jul. 19, 2007 page 505 of 532
REJ09B0397-0300
IRR1—Interrupt request register 1
H'F6
System control
Bit
Initial value
Read/Write
7
IRRTA
0
R/W
*
2
6
IRRS1
*
1
0
R/W
*
2
5
⎯
1
⎯
4
IRRI4
0
R/W
*
2
3
IRRI3
0
R/W
*
2
0
IRRI0
0
R/W
*
2
2
IRRI2
*
1
0
R/W
*
2
1
IRRI1
0
R/W
*
2
Timer A interrupt request flag
0
[Clearing condition]
When IRRTA = 1, it is cleared by writing 0
1
[Setting condition]
When the timer A counter overflows from H'FF to H'00
SCI1 interrupt request flag
0
[Clearing condition]
When IRRS1 = 1, it is cleared by writing 0
1
[Setting condition]
When an SCI1 transfer is completed
IRQ to IRQ interrupt request flag
0
[Clearing conditions]
When IRRI4 = 1, it is cleared by writing 0
When 0 is written to IRRI4 when IRRI4 = 1
The same also applies to IRRI3—IRRI0
1
[Setting conditions]
When pin
IRQ
is set to interrupt input and the designated signal edge is
detected
When pin
IRQ
4
is set to interrupt input and the designated edge is input at this pin
The same also applies to IRRI3—IRRI0
4
0
4
Notes: 1. IRRS1 and IRRI2 are functions of the H8/3857 Group only.
In the H8/3854 Group these bits are reserved, and are always 0.
2. Only a write of 0 for flag clearing is possible.
Summary of Contents for F-ZTAT H8 Series
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