Renesas F-ZTAT H8 Series, Hardware Manual

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8. I/O Ports
Rev.3.00 Jul. 19, 2007 page 204 of 532
REJ09B0397-0300
8.8.2 Register Configuration and Description
Table 8.20 shows the port A register configuration.
Table 8.20 Port A Registers
Name Abbr. R/W Initial Value Address
Port data register A PDRA R/W H'F0 H'FFDD
Port control register A PCRA W H'F0 H'FFED
Port Data Register A (PDRA)
Bit 7 6 5 4 3 2 1 0
⎯ ⎯ ⎯ ⎯
PA
3
PA
2
PA
1
PA
0
Initial value 1 1 1 1 0 0 0 0
Read/Write
⎯ ⎯ ⎯ ⎯
R/W R/W R/W R/W
PDRA is an 8-bit register that stores data for port A pins PA
3
to PA
0
. If port A is read while PCRA
bits are set to 1, the values stored in PDRA are read. If port A is read while PCRA bits are cleared
to 0, the pin states are read.
Upon reset, PDRA is initialized to H'F0.
Port Control Register A (PCRA)
Bit 7 6 5 4 3 2 1 0
⎯ ⎯ ⎯ ⎯
PCRA
3
PCRA
2
PCRA
1
PCRA
0
Initial value 1 1 1 1 0 0 0 0
Read/Write
⎯ ⎯ ⎯ ⎯
W W W W
PCRA is an 8-bit register for controlling whether each of the port A pins PA
3
to PA
0
functions as
an input or output pin. Setting a PCRA bit to 1 makes the corresponding pin an output pin, while
clearing the bit to 0 makes the pin an input pin.
Upon reset, PCRA is initialized to H'F0.
PCRA is a write-only register. All bits are read as 1.