Appendix A CPU Instruction Set
Rev.3.00 Jul. 19, 2007 page 449 of 532
REJ09B0397-0300
Addressing
Mode/
Instruction Length (Bytes)
Condition Code
Mnemonic
Operand Siz
e
Operation
#xx:
8/16
Rn
@Rn
@(d:16,
Rn)
@–Rn/@Rn+
@aa:
8/16
@(d:8,
PC)
@@aa
Implied
I
H
N
Z
V
C
No.
of States
JSR @@aa:8
⎯
SP–2
→
SP
PC
→
@SP
PC
←
@aa:8
2
⎯
⎯
⎯
⎯
⎯
⎯
8
RTS
⎯
PC
←
@SP
SP+2
→
SP
2
⎯
⎯
⎯
⎯
⎯
⎯
8
RTE
⎯
CCR
←
@SP
SP+2
→
SP
PC
←
@SP
SP+2
→
SP
2
10
SLEEP
⎯
Transit to power-down
state
2
⎯
⎯
⎯
⎯
⎯
⎯
2
LDC #xx:8, CCR
B #xx:8
→
CCR
2
2
LDC Rs, CCR
B Rs8
→
CCR
2
2
STC CCR, Rd
B CCR
→
Rd8
2
⎯
⎯
⎯
⎯
⎯
⎯
2
ANDC #xx:8, CCR
B CCR
∧
#xx:8
→
CCR
2
2
ORC #xx:8, CCR
B CCR
∨
#xx:8
→
CCR
2
2
XORC #xx:8, CCR
B CCR
⊕
#xx:8
→
CCR
2
2
NOP
⎯
PC
←
PC+2
2
⎯
⎯
⎯
⎯
⎯
⎯
2
EEPMOV
⎯
if R4L
≠
0
Repeat @R5
→
@R6
R5+1
→
R5
R6+1
→
R6
R4L–1
→
R4L
Until R4L = 0
else next;
4
⎯
⎯
⎯
⎯
⎯
⎯
(4)
Notes: (1) Set to 1 when there is a carry or borrow from bit 11; otherwise cleared to 0.
(2) If the result is zero, the previous value of the flag is retained; otherwise the flag is
cleared to 0.
(3) Set to 1 if decimal adjustment produces a carry; otherwise retains value prior to
arithmetic operation.
(4) The number of states required for execution is 4n + 9 (n = value of R4L).
(5) Set to 1 if the divisor is negative; otherwise cleared to 0.
(6) Set to 1 if the divisor is zero; otherwise cleared to 0.
Summary of Contents for F-ZTAT H8 Series
Page 6: ...Rev 3 00 Jul 19 2007 page iv of xxiv REJ09B0397 0300...
Page 194: ...7 RAM Rev 3 00 Jul 19 2007 page 168 of 532 REJ09B0397 0300...
Page 234: ...8 I O Ports Rev 3 00 Jul 19 2007 page 208 of 532 REJ09B0397 0300...
Page 274: ...9 Timers Rev 3 00 Jul 19 2007 page 248 of 532 REJ09B0397 0300...
Page 352: ...12 A D Converter Rev 3 00 Jul 19 2007 page 326 of 532 REJ09B0397 0300...
Page 561: ......
