9. Timers
Rev.3.00 Jul. 19, 2007 page 245 of 532
REJ09B0397-0300
Bit 0—Watchdog Timer Reset (WRST):
Bit 0 indicates that TCW has overflowed and an
internal reset signal has been generated. The internal reset signal generated by the overflow resets
the entire chip.
WRST is cleared by a reset via the
RES
pin or by a 0 write by software.
Bit 0: WRST Description
0
[Clearing conditions]
(initial value)
•
Reset by
RES
pin
•
When 0 is written to WRST while writing 0 to B0WI when TCSRWE = 1
1 [Setting
condition]
When TCW overflows and an internal reset signal is generated
Timer Counter W (TCW)
TCW7
TCW2
TCW1
TCW0
TCW6
TCW5
TCW4
TCW3
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
Initial value
Read/Write
TCW is an 8-bit read/write up-counter that is incremented by an input internal clock. The TCW
value can be read or written by the CPU at any time.
When TCW overflows (from H'FF to H'00), an internal reset signal is generated and WRST in
TCSRW is set to 1. Upon reset, TCW is initialized to H'00.
Timer Mode Register W (TMW)
⎯
CKS2
7
6
5
4
3
2
1
0
1
1
⎯
⎯
1
⎯
⎯
1
⎯
⎯
1
⎯
⎯
1
⎯
R/W
CKS1
1
R/W
CKS0
1
R/W
Bit
Initial value
Read/Write
TMW is an 8-bit read/write register that selects the input clock.
Upon reset, TMW is initialized to H'FF.
Bits 7 to 3—Reserved Bits:
Bits 7 to 3 are reserved; they are always read as 1 and cannot be
modified.
Summary of Contents for F-ZTAT H8 Series
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