6. ROM
Rev.3.00 Jul. 19, 2007 page 144 of 532
REJ09B0397-0300
End of erasing
START
Set SWE bit in FLMCR1
Set ESU bit in FLMCR2
Set E bit in FLMCR1
Wait (x)
μ
s
Wait (y)
μ
s
n = 1
Set EBR
Enable WDT
*
2
*
4
*
2
Wait (z) ms
*
2
Wait (
α
)
μ
s
*
2
Wait (
β
)
μ
s
*
2
Wait (
γ
)
μ
s
Set block start address
as verify address
*
2
Wait (
ε
)
μ
s
*
2
Wait (
η
)
μ
s
*
2
*
2
*
2
*
3
*
5
Start of erase
Clear E bit in FLMCR1
Clear ESU bit in FLMCR2
Set EV bit in FLMCR1
H'FF dummy write to verify address
Read verify data
Clear EV bit in FLMCR1
Wait (
η
)
μ
s
Clear EV bit in FLMCR1
Clear SWE bit in FLMCR1
Disable WDT
Erase halted
*
1
Verify data =
all 1?
Last address
of block?
End of erasing of
all erase blocks?
Erase failure
Clear SWE bit in FLMCR1
n
≥
N?
No
No
No
No
Yes
Yes
Yes
Yes
Notes:
Prewriting (setting erase block data to all 1) is not necessary.
The values of x, y, z,
α
,
β
,
γ
,
ε
,
η
, and N are shown in section 15.2.6, Flash Memory Characteristics.
Verify data is read in 16-bit (word) units.
Set only one bit in EBR; two or more bits must not be set.
Erasing is performed in block units. To erase multiple blocks, each block must be erased in turn.
1.
2.
3.
4.
5.
Increment
address
n
←
n + 1
Figure 6.13 Erase/Erase-Verify Flowchart (Single-Block Erase)
Summary of Contents for F-ZTAT H8 Series
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