Renesas F-ZTAT H8 Series, Hardware Manual

Page: 313 / 562

10. Serial Communication Interface
Rev.3.00 Jul. 19, 2007 page 287 of 532
REJ09B0397-0300
Figure 10.9 shows a typical flow chart for SCI3 initialization.
Start
Clear TE and RE to 0 in SCR3
Select communication format in SMR
Set BRR value
Has a 1-bit
interval elapsed?
Set bits RIE, TIE, TEIE, and MPIE
in SCR3, and set TE or RE to 1
2
3
4
1.
2.
3.
4.
Select the clock in serial control re g ister 3
(SCR3). Other bits must be cleared to 0.
If clock output is selected in asynchronous
mode, a clock si
g nal will be output as soon
as CKE1 and CKE0 have been set.
If clock output is selected for reception in
synchronous mode, a clock si
g nal will be
output as soon as bits CKE1 and CKE0,
and bit RE, are set to 1.
Set the transmit/receive format in the serial
mode re
g ister (SMR).
Set the bit rate re g ister (BRR) to the value
g ivin g the desired bit rate.
This step is not required when an external
clock source is used.
Wait for at least a 1-bit interval, then set
bits RIE, TIE, TEIE, and MPIE, and set bit
TE or RE in SCR3 to 1. Settin
g TE or RE
enables SCI3 to use the TXD or RXD pin.
The initial states in asynchronous mode
are the mark transmit state and the idle
receive state (waitin
g for a start bit).
No
Yes
Wait
End
1
Set bits CKE1 and CKE0
Figure 10.9 Typical Flow Chart when SCI3 Is Initialized