14. Dot Matrix LCD Controller (H8/3854 Group)
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REJ09B0397-0300
Reading for Display
Reads for LCD display are performed asynchronously with respect to accesses by the CPU.
However, since simultaneous accesses would corrupt data in the RAM, arbitration is carried out
within the chip. Basically, accesses by the CPU have priority, and reads for display are performed
in the intervals between CPU accesses.
RS
R/
W
STRB
Input data
Output data
Address
H'02
[n, m]
H'04
[n, m]
[n, m+1]
[n, m+2]
data
[n, m+1]
data
[n, m]
[
*
,
*
]
Figure 14.7 Memory Read Procedure
Summary of Contents for F-ZTAT H8 Series
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