2. CPU
Rev.3.00 Jul. 19, 2007 page 34 of 532
REJ09B0397-0300
2.4 Addressing
Modes
2.4.1 Addressing
Modes
The H8/300L CPU supports the eight addressing modes listed in table 2.1. Each instruction uses a
subset of these addressing modes.
Table 2.1
Addressing Modes
No. Address
Modes
Symbol
1 Register
direct
Rn
2 Register
indirect
@Rn
3
Register indirect with displacement @(d:16,
Rn)
4
Register indirect with post-increment
Register indirect with pre-decrement
@Rn+
@
−
Rn
5
Absolute address
@aa:8 or @aa:16
6
Immediate
#xx:8 or #xx:16
7
Program-counter relative
@(d:8, PC)
8 Memory
indirect
@@aa:8
1. Register Direct—Rn:
The register field of the instruction specifies an 8- or 16-bit general
register containing the operand.
Only the MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits
×
8 bits), and
DIVXU (16 bits ÷ 8 bits) instructions have 16-bit operands.
2. Register Indirect—@Rn:
The register field of the instruction specifies a 16-bit general
register containing the address of the operand in memory.
3. Register Indirect with Displacement—@(d:16, Rn):
The instruction has a second word
(bytes 3 and 4) containing a 16-bit displacement which is added to the contents of the specified
general register (16-bit) to obtain the operand address in memory.
This mode is used only in MOV instructions. For the MOV.W instruction, the resulting address
must be even.
Summary of Contents for F-ZTAT H8 Series
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