3. Exception Handling
Rev.3.00 Jul. 19, 2007 page 90 of 532
REJ09B0397-0300
PC
PC
R1L
PC
SP
SP
SP
H'FEFC
H'FEFD
H'FEFF
→
→
→
H
L
L
MOV. B R1L, @–R7
SP set to H'FEFF
Stack accessed beyond SP
BSR instruction
Contents of PC are lost
H
Legend:
PC
H
:
PC
L
:
R1L:
SP:
Upper byte of program counter
Lower byte of program counter
General register R1L
Stack pointer
Figure 3.6 Operation when Odd Address Is Set in SP
When CCR contents are saved to the stack during interrupt exception handling or restored when
RTE is executed, this also takes place in word size. Both the upper and lower bytes of word data
are saved to the stack; on return, the even address contents are restored to CCR while the odd
address contents are ignored.
3.4.2
Notes on Rewriting Port Mode Registers
When a port mode register is rewritten to switch the functions of external interrupt pins, the
following points should be observed.
When an external interrupt pin function is switched by rewriting the port mode register that
controls these pins (
IRQ
4
,
IRQ
3
,
IRQ
2
*,
IRQ
1
,
IRQ
0
, and
WKP
7
to
WKP
0
), the interrupt request flag
may be set to 1 at the time the pin function is switched, even if no valid interrupt is input at the
pin. Be sure to clear the interrupt request flag to 0 after switching pin functions. Table 3.5 shows
the conditions under which interrupt request flags are set to 1 in this way.
Note: * Applies to the H8/3857 Group; not provided in the H8/3854 Group.
Summary of Contents for F-ZTAT H8 Series
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