Appendix B Internal I/O Registers
Rev.3.00 Jul. 19, 2007 page 503 of 532
REJ09B0397-0300
IENR1—Interrupt enable register 1
H'F3
System control
Bit
Initial value
Read/Write
7
IENTA
0
R/W
6
IENS1
*
0
R/W
5
IENWP
0
R/W
4
IEN4
0
R/W
3
IEN3
0
R/W
0
IEN0
0
R/W
2
IEN2
*
0
R/W
1
IEN1
0
R/W
IRQ to IRQ interrupt enable
0
Disables interrupt request
IRQ
1
4
n
0
Enables interrupt request
IRQ
n
Wakeup interrupt enable
0
Disables interrupt requests from
WKP
to
WKP
1
7
0
Enables interrupt requests from
WKP
to
WKP
7
0
SCI1 interrupt enable
0
Disables SCI1 interrupts
1
Enables SCI1 interrupts
Timer A interrupt enable
0
Disables timer A interrupts
1
Enables timer A interrupts
Note: n = 4 to 0
Note:
*
IENS1 and IEN2 are functions of the H8/3857 Group only.
In the H8/3854 Group these bits are reserved, and must always be cleared to 0.
Summary of Contents for F-ZTAT H8 Series
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