3. Exception Handling
Rev.3.00 Jul. 19, 2007 page 87 of 532
REJ09B0397-0300
PC and CCR
saved to stack
SP (R7)
SP – 1
SP – 2
SP – 3
SP – 4
Stack area
SP + 4
SP + 3
SP + 2
SP + 1
SP (R7)
Even address
Prior to start of interrupt
exception handling
After completion of interrupt
exception handling
Legend:
PC
H
:
PC
L
:
CCR:
SP:
Upper 8 bits of program counter (PC)
Lower 8 bits of program counter (PC)
Condition code register
Stack pointer
*
Ignored on return from interrupt.
Notes:
CCR
CCR
*
PC
H
PC
L
PC shows the address of the first instruction to be executed upon
return from the interrupt handling routine.
Register contents must always be saved and restored by word access,
starting from an even-numbered address.
Figure 3.4 Stack State after Completion of Interrupt Exception Handling
Figure 3.5 shows a typical interrupt sequence where the program area is in the on-chip ROM and
the stack area is in the on-chip RAM.
Summary of Contents for F-ZTAT H8 Series
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