Appendix B Internal I/O Registers
Rev.3.00 Jul. 19, 2007 page 477 of 532
REJ09B0397-0300
SDRU—Serial data register U
H'A2
SCI1
(H8/3857 Group only)
Bit
Initial value
Read/Write
7
SDRU7
Undefined
R/W
6
SDRU6
Undefined
R/W
5
SDRU5
Undefined
R/W
4
SDRU4
Undefined
R/W
3
SDRU3
Undefined
R/W
0
SDRU0
Undefined
R/W
2
SDRU2
Undefined
R/W
1
SDRU1
Undefined
R/W
Used to set transmit data and store receive data
8-bit transfer mode:
16-bit transfer mode:
Not used
Upper 8 bits of data
SDRL—Serial data register L
H'A3
SCI1
(H8/3857 Group only)
Bit
Initial value
Read/Write
7
SDRL7
Undefined
R/W
6
SDRL6
Undefined
R/W
5
SDRL5
Undefined
R/W
4
SDRL4
Undefined
R/W
3
SDRL3
Undefined
R/W
0
SDRL0
Undefined
R/W
2
SDRL2
Undefined
R/W
1
SDRL1
Undefined
R/W
Used to set transmit data and store receive data
8-bit transfer mode:
16-bit transfer mode:
8-bit data
Lower 8 bits of data
Summary of Contents for F-ZTAT H8 Series
Page 6: ...Rev 3 00 Jul 19 2007 page iv of xxiv REJ09B0397 0300...
Page 194: ...7 RAM Rev 3 00 Jul 19 2007 page 168 of 532 REJ09B0397 0300...
Page 234: ...8 I O Ports Rev 3 00 Jul 19 2007 page 208 of 532 REJ09B0397 0300...
Page 274: ...9 Timers Rev 3 00 Jul 19 2007 page 248 of 532 REJ09B0397 0300...
Page 352: ...12 A D Converter Rev 3 00 Jul 19 2007 page 326 of 532 REJ09B0397 0300...
Page 561: ......
