14. Dot Matrix LCD Controller (H8/3854 Group)
Rev.3.00 Jul. 19, 2007 page 383 of 532
REJ09B0397-0300
Table 14.3 Register Settings, Division Ratios, and Frame Frequencies at Each Display Duty
Display Duty 1/N
1/8 1/16
Subclock Frequency f
W
(kHz)
32.768 38.4
32.768 38.4
FS2
FS1
FS0
Division
ratio r
Frame Frequency f
F
(Hz)
0 0 0 2 2048.0
2400.0
1024.0
1200.0
1 4 1024.0
1200.0
512.0
600.0
1 0 8 512.0
600.0
256.0
300.0
1
16
256.0 300.0
128.0 150.0
1 0 0 32
128.0
150.0
64.0
75.0
1
64 64.0 75.0
32.0 37.5
1
0
128 32.0 37.5
16.0 18.8
1
Setting
prohibited
Setting
prohibited
Setting
prohibited
Setting
prohibited
Setting
prohibited
14.2.6
Display Data Register (LR4)
7
D7
Undefined
R/W
6
D6
Undefined
R/W
5
D5
Undefined
R/W
4
D4
Undefined
R/W
3
D3
Undefined
R/W
0
D0
Undefined
R/W
2
D2
Undefined
R/W
1
D1
Undefined
R/W
Bit
Initial value
Read/Write
LR4 is an 8-bit read/write register used to perform read/write access to the display memory
specified by XA2 to XA0 and YA3 to YA0 in LR2.
In a write to display memory, the write is performed directly to the display memory via this
register. In a read, the data is temporarily latched into this register before being output to the bus.
After a reset, the display memory and LR4 contents are undefined.
Summary of Contents for F-ZTAT H8 Series
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Page 194: ...7 RAM Rev 3 00 Jul 19 2007 page 168 of 532 REJ09B0397 0300...
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