Renesas F-ZTAT H8 Series, Hardware Manual

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10. Serial Communication Interface
Rev.3.00 Jul. 19, 2007 page 255 of 532
REJ09B0397-0300
Bit 5—Overrun Error Flag (ORER): When an external clock is used, bit 5 indicates the
occurrence of an overrun error. If a clock pulse is input after transfer completion, this bit is set to 1
indicating an overrun. If noise occurs during a transfer, causing an extraneous pulse to be
superimposed on the normal serial clock, incorrect data may be transferred.
Bit 5: ORER Description
0 Clearing condition:
After reading ORER = 1, cleared by writing 0 to ORER (initial value)
1 Setting condition:
Set if a clock pulse is input after transfer is complete, when an external clock is
used
Bits 4 to 2—Reserved Bits: Bits 4 to 2 are reserved; they are always read as 0, and cannot be
modified.
Bit 1—Reserved Bit: Bit 1 is reserved; it should always be cleared to 0.
Bit 0—Start Flag (STF): Bit 0 controls the start of a transfer. Setting this bit to 1 causes SCI1 to
start transferring data.
This bit remains set to 1 during transfer or while waiting for a start bit, and is cleared to 0 upon
completion of the transfer.
Bit 0: STF Description
0 Read: Indicates that transfer is stopped (initial value)
Write: Invalid
1 Read: Indicates transfer in progress
Write: Starts a transfer operation
Serial Data Register U (SDRU)
Bit 7 6 5 4 3 2 1 0
SDRU7 SDRU6 SDRU5 SDRU4 SDRU3 SDRU2 SDRU1 SDRU0
Initial value
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
SDRU is an 8-bit read/write register. It is used as the data register for the upper 8 bits in 16-bit
transfer (SDRL is used for the lower 8 bits).