2. CPU
Rev.3.00 Jul. 19, 2007 page 54 of 532
REJ09B0397-0300
Legend:
op:
rn:
IMM:
Operation field
Register field
Immediate data
15
0
8
7
op
RTE, SLEEP, NOP
15
0
8
7
op
rn
LDC, STC (Rn)
15
0
8
7
op
IMM
ANDC, ORC,
XORC, LDC (#xx:8)
Figure 2.9 System Control Instruction Codes
2.5.8
Block Data Transfer Instruction
Table 2.11 describes the block data transfer instruction. Figure 2.10 shows its object code format.
Table 2.11 Block Data Transfer Instruction
Instruction Size Function
EEPMOV
⎯
if
R4L
≠
0 then
repeat
@R5+
→
@R6+
R4L – 1
→
R4L
until
R4L = 0
else next;
Block transfer instruction. Transfers the number of bytes specified by
R4L, from locations starting at the address specified by R5, to locations
starting at the address specified by R6. On completion of the transfer,
the next instruction is executed.
Certain precautions are required in using the EEPMOV instruction. See section 2.9.3, Notes on
Use of the EEPMOV Instruction, for details.
Summary of Contents for F-ZTAT H8 Series
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