Appendix B Internal I/O Registers
Rev.3.00 Jul. 19, 2007 page 502 of 532
REJ09B0397-0300
IEGR—IRQ edge select register
H'F2
System control
Bit
Initial value
Read/Write
7
⎯
1
⎯
6
⎯
1
⎯
5
⎯
1
⎯
4
IEG4
0
R/W
3
IEG3
0
R/W
0
IEG0
0
R/W
2
IEG2
*
0
R/W
1
IEG1
0
R/W
IRQ edge select
0
Falling edge of
IRQ
pin input is detected
1
Rising edge of
IRQ
pin input is detected
0
0
0
IRQ edge select
0
Falling edge of
IRQ
/TMIB pin input is detected
1
Rising edge of
IRQ
/TMIB pin input is detected
1
1
1
IRQ edge select
0
Falling edge of
IRQ
/TMIC pin input is detected
1
Rising edge of
IRQ
/TMIC pin input is detected
2
2
2
IRQ edge select
0
Falling edge of
IRQ
/TMIF pin input is detected
1
Rising edge of
IRQ
/TMIF pin input is detected
3
3
3
IRQ edge select
0
Falling edge of
IRQ
/
ADTRG
pin input is detected
1
Rising edge of
IRQ
/
ADTRG
pin input is detected
4
4
4
Note:
*
IEG2 is a function of the H8/3857 Group only.
In the H8/3854 Group this bit is reserved, and must always be cleared to 0.
Summary of Contents for F-ZTAT H8 Series
Page 6: ...Rev 3 00 Jul 19 2007 page iv of xxiv REJ09B0397 0300...
Page 194: ...7 RAM Rev 3 00 Jul 19 2007 page 168 of 532 REJ09B0397 0300...
Page 234: ...8 I O Ports Rev 3 00 Jul 19 2007 page 208 of 532 REJ09B0397 0300...
Page 274: ...9 Timers Rev 3 00 Jul 19 2007 page 248 of 532 REJ09B0397 0300...
Page 352: ...12 A D Converter Rev 3 00 Jul 19 2007 page 326 of 532 REJ09B0397 0300...
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