13. Dot Matrix LCD Controller (H8/3857 Group)
Rev.3.00 Jul. 19, 2007 page 343 of 532
REJ09B0397-0300
13.3.2 CPU
Interface
The LCD controller's registers are not included in the memory map shown in figure 2.16 (a). They
are controlled from the CPU by means of chip-internal LCD pins DB7 to DB0, RS, R/
W
, and
STRB, via chip-internal I/O ports 9 and A. The pin configuration is shown in table 13.5, and an
example of the timing for access to registers in the LCD controller is shown in figure 13.3. For
information on port 9 and port A, see the descriptions in section 8, I/O Ports.
Table 13.5 Pin Configuration
Pin Name
Abbr.
I/O
Function
Data bus
pins
DB7 to DB0
I/O
When R/
W
= 0, these pins input data to be written to a register;
when R/
W
= 1, they output data read from a register
Register
selector pin
RS
Input When R/S = 0, the index register is selected; when RS = 1, a
control register is selected
Read/write
select pin
R/
W
Input
When
R/
W
= 0, write access is selected; when R/
W
= 1, read
access is selected
Strobe pin
STRB
Input At the fall of STRB, read or write access, as selected by R/
W
,
is performed on the register selected by RS
Writing to Index Register
When RS and R/
W
are both cleared to 0, data DB7 to DB0 is written to the index register (IR) at
the falling edge of STRB. Do not change RS or R/
W
at the fall of STRB.
Reading and Writing to Control Registers
To access a control register, data indicating the number of the register to be accessed must be
written to the index register (IR) before making the access. The register number data to be written
to IR is shown in table 13.2. As the register number written to IR is retained until IR is written to
again, if the same control register is accessed repeatedly, it is not necessary to write to IR each
time.
In a write to a control register, when RS has been set to 1 and R/
W
cleared to 0, data DB7 to DB0
is written to the control register specified by the index register (IR) at the falling edge of STRB.
Except for the display data register (LR4), control registers cannot be read. In a read of LR4, when
the LR4 register number is written to the index register (IR), and RS and R/
W
are both set to 1,
DB7 to DB0 are set to output mode, and the display memory data at the address specified by the
address register (LR2) is output from DB7 to DB0 at the rising edge of STRB. If a read is also
performed in the next cycle, the data output is held until the next rise of STRB, but if a write is
Summary of Contents for F-ZTAT H8 Series
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