3. Exception Handling
Rev.3.00 Jul. 19, 2007 page 84 of 532
REJ09B0397-0300
Interrupts IRQ
0
to IRQ
4
:
Interrupts IRQ
0
to IRQ
4
are requested by into pins inputs to
IRQ
0
to
IRQ
4
. These interrupts are detected by either rising edge sensing or falling edge sensing,
depending on the settings of bits IEG0 to IEG4 in the edge select register (IEGR). The IRQ
2
interrupt is a function of the H8/3857 Group only, and is not provided in the H8/3854 Group.
When these pins are designated as pins
IRQ
0
to
IRQ
4
in port mode registers 1 and 2 (PMR1 and
PMR2) and the designated edge is input, the corresponding bit in IRR1 is set to 1, requesting an
interrupt. Interrupts IRQ
0
to IRQ
4
can be disabled by clearing bits IEN0 to IEN4 in IENR1 to 0.
All interrupts can be masked by setting the I bit in CCR to 1.
When IRQ
0
to IRQ
4
interrupt exception handling is initiated, the I bit is set to 1. Vector numbers 4
to 8 are assigned to interrupts IRQ
0
to IRQ
4
. The order of priority is from IRQ
0
(high) to IRQ
4
(low). Table 3.2 gives details. In the H8/3854 Group, exception handling vector number 6 is
reserved.
3.3.4 Internal
Interrupts
There are 16 internal interrupts that can be requested by the on-chip peripheral modules in the
H8/3857 Group, and 14 in the H8/3854 Group. When a peripheral module requests an interrupt,
the corresponding bit in IRR1 or IRR2 is set to 1. Individual interrupt requests can be disabled by
clearing the corresponding bit in IENR1 or IENR2 to 0. All interrupts can be masked by setting
the I bit in CCR to 1. When an internal interrupt request is accepted, the I bit is set to 1. Vector
numbers 10 to 20 are assigned to these interrupts. Table 3.2 shows the order of priority of
interrupts from on-chip peripheral modules. In the H8/3854 Group, exception handling vector
numbers 10 and 13 are reserved.
3.3.5 Interrupt
Operations
Interrupts are controlled by an interrupt controller. Figure 3.2 shows a block diagram of the
interrupt controller. Figure 3.3 shows the flow up to interrupt acceptance.
Interrupt operation is described as follows.
•
When an interrupt condition is met while the interrupt enable register bit is set to 1, an
interrupt request signal is sent to the interrupt controller.
•
When the interrupt controller receives an interrupt request, it sets the interrupt request flag.
•
From among the interrupts with interrupt request flags set to 1, the interrupt controller selects
the interrupt request with the highest priority and holds the others pending. (Refer to
table 3.2 for a list of interrupt priorities.)
•
The interrupt controller checks the I bit of CCR. If the I bit is 0, the selected interrupt request
is accepted; if the I bit is 1, the interrupt request is held pending.
Summary of Contents for F-ZTAT H8 Series
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