Appendix B Internal I/O Registers
Rev.3.00 Jul. 19, 2007 page 473 of 532
REJ09B0397-0300
TCSRW—Timer control/status register W
H'90
Flash memory
(On-chip flash memory version only)
Bit
Initial value
Read/Write
:
:
:
7
1
R
6
0
R/(W)
*
5
1
R
4
0
R/(W)
*
3
1
R
2
0
R/(W)
*
1
1
R
0
B6WI
TCWE
B4WI TCSRWE B2WI
WDON
B0WI
WRST
0
R/(W)
*
Writing to bit 0 is enabled
Writing to bit 0 is disabled
Bit 0 write inhibit
0
1
Watchdog timer operation is disabled
Watchdog timer operation is enabled
Watchdog timer on
0
1
Writing to bit 2 is enabled
Writing to bit 2 is disabled
Bit 2 write inhibit
0
1
Writing to bits 2 and 0 is disabled
Writing to bits 2 and 0 is enabled
Timer control/status register W write enable
0
1
Writing to bit 4 is enabled
Writing to bit 4 is disabled
Bit 4 write inhibit
0
1
Writing of data to TCW is disabled
Writing of data to TCW is enabled
Timer counter W write enable
0
1
Writing to bit 6 is enabled
Writing to bit 6 is disabled
Bit 6 write inhibit
0
1
Note:
*
Can be written to only when the write condition is satisfied.
[Clearing conditions]
• Reset by
RES
pin
• When 0 is written to WRST while writing 0 to
B0WI when TCSRWE = 1
[Setting condition]
When TCW overflows and an internal reset
signal is generated
Watchdog timer reset
0
1
Summary of Contents for F-ZTAT H8 Series
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Page 194: ...7 RAM Rev 3 00 Jul 19 2007 page 168 of 532 REJ09B0397 0300...
Page 234: ...8 I O Ports Rev 3 00 Jul 19 2007 page 208 of 532 REJ09B0397 0300...
Page 274: ...9 Timers Rev 3 00 Jul 19 2007 page 248 of 532 REJ09B0397 0300...
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