Renesas F-ZTAT H8 Series, Hardware Manual

Page: 470 / 562

Appendix A CPU Instruction Set
Rev.3.00 Jul. 19, 2007 page 444 of 532
REJ09B0397-0300
Addressing Mode/
Instruction Length (Bytes) Condition Code
Mnemonic
Operand Siz
e
Operation
#xx:
8/16
Rn @Rn @(d:16,
Rn)
@–Rn/@Rn+ @aa:
8/16
@(d:8,
PC)
@@aa Implied
I H N Z V C
No.
of States
PUSH Rs W SP–2
→
SP
Rs16
→
@SP
2
⎯ ⎯
0
⎯
6
ADD.B #xx:8, Rd B Rd8+#xx:8
→
Rd8 2
⎯
2
ADD.B Rs, Rd B Rd8+Rs8
→
Rd8 2
⎯
2
ADD.W Rs, Rd W Rd16+Rs16
→
Rd16 2
⎯
(1) 2
ADDX.B #xx:8, Rd B Rd8+#xx:8 +C
→
Rd8 2
⎯
(2) 2
ADDX.B Rs, Rd B Rd8+Rs8 +C
→
Rd8 2
⎯
(2) 2
ADDS.W #1, Rd W Rd16+1
→
Rd16 2
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
2
ADDS.W #2, Rd W Rd16+2
→
Rd16 2
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
2
INC.B Rd B Rd8+1
→
Rd8 2
⎯ ⎯ ⎯
2
DAA.B Rd B Rd8 decimal adjust
→
Rd8 2
⎯
* * (3) 2
SUB.B Rs, Rd B Rd8–Rs8
→
Rd8 2
⎯
2
SUB.W Rs, Rd W Rd16–Rs16
→
Rd16 2
⎯
(1) 2
SUBX.B #xx:8, Rd B Rd8–#xx:8 –C
→
Rd8 2
⎯
(2) 2
SUBX.B Rs, Rd B Rd8–Rs8 –C
→
Rd8 2
⎯
(2) 2
SUBS.W #1, Rd W Rd16–1
→
Rd16 2
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
2
SUBS.W #2, Rd W Rd16–2
→
Rd16 2
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
2
DEC.B Rd B Rd8–1
→
Rd8 2
⎯ ⎯ ⎯
2
DAS.B Rd B Rd8 decimal adjust
→
Rd8 2
⎯
* *
⎯
2
NEG.B Rd B 0–Rd
→
Rd 2
⎯
2
CMP.B #xx:8, Rd B Rd8–#xx:8 2
⎯
2
CMP.B Rs, Rd B Rd8–Rs8 2
⎯
2
CMP.W Rs, Rd W Rd16–Rs16 2
⎯
(1) 2
MULXU.B Rs, Rd B Rd8
×
Rs8
→
Rd16 2
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
14