6. ROM
Rev.3.00 Jul. 19, 2007 page 130 of 532
REJ09B0397-0300
Bit 0—Program Setup (PSU)
*
:
Bit 0 prepares for a transition to program mode. Set this bit to 1
before setting the P bit in FLMCR1. (Do not set the SWE, ESU, EV, PV, E, or P bit at the same
time.)
Bit 0: PSU
Description
0
Program setup cleared
(initial value)
1 Program
setup
[Setting condition]
When FWE = 1 and SWE = 1
Note: * Do not set multiple bits simultaneously.
Do not cut V
CC
while a bit is set.
6.3.3
Erase Block Register (EBR)
Bit
7 6 5 4 3 2 1 0
⎯
EB6 EB5 EB4 EB3 EB2 EB1 EB0
Initial
value 0 0 0 0 0 0 0 0
Read/Write
⎯
R/W R/W R/W R/W R/W R/W R/W
EBR is a register that specifies the flash memory erase area, block by block. Bits 6 to 0 of EBR are
read/write bits. EBR is initialized to H'00 by a reset, in standby mode, when a low level is input to
the FWE pin, and when a high level is input to the FWE pin while the SWE bit in FLMCR1 is
cleared to 0. When a bit in EBR is set to 1, the corresponding block can be erased. Other blocks
are erase-protected. As erasing is carried out on a block-by-block basis, only one bit in EBR
should be set at a time (more than one bit must not be set).
The flash memory block configuration is shown in table 6.4. To erase the entire flash memory,
individual blocks must be erased in succession.
Summary of Contents for F-ZTAT H8 Series
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Page 194: ...7 RAM Rev 3 00 Jul 19 2007 page 168 of 532 REJ09B0397 0300...
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