9. Timers
Rev.3.00 Jul. 19, 2007 page 242 of 532
REJ09B0397-0300
An overflow period of 1 to 256 times the selected clock can be set.
Block Diagram
Figure 9.8 shows a block diagram of the watchdog timer.
φ
Internal reset signal
PSS
TCW
TMW
TCSRW
Internal data bus
Legend:
TCSRW
TCW
PSS
TMW
: Timer control/status register W
: Timer counter W
: Prescaler S
: Timer mode register W
Figure 9.8 Block Diagram of Watchdog Timer
Register Configuration
Table 9.14 shows the watchdog timer register configuration. These registers are valid only in the
F-ZTAT version. In the mask ROM version, read accesses to the corresponding addresses will
always return 1, and writes are invalid.
Table 9.14 Watchdog Timer Registers
Name Abbr.
R/W
Initial
Value
Address
Timer control/status register W
TCSRW
R/W
H'AA
H'FF90
Timer counter W
TCW
R/W
H'00
H'FF91
Timer mode register W
TMW
R/W
H'FF
H'FF92
Summary of Contents for F-ZTAT H8 Series
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