3. Exception Handling
Rev.3.00 Jul. 19, 2007 page 76 of 532
REJ09B0397-0300
Bit 3—IRQ
3
Edge Select (IEG3):
Bit 3 selects the input sensing of pin
IRQ
3
/TMIF.
Bit 3: IEG3
Description
0
Falling edge of
IRQ
3
/TMIF pin input is detected
(initial value)
1
Rising edge of
IRQ
3
/TMIF pin input is detected
Bit 2—IRQ
2
Edge Select (IEG2):
Bit 2 is used in the H8/3857 Group to select the input sensing
of pin
IRQ
2
/TMIC. In the H8/3854 Group, this bit must always be cleared to 0.
Bit 2: IEG2
Description
0
Falling edge of
IRQ
2
/TMIC pin input is detected
(initial value)
1
Rising edge of
IRQ
2
/TMIC pin input is detected
Bit 1—IRQ
1
Edge Select (IEG1):
Bit 1 selects the input sensing of pin
IRQ
1
/TMIB.
Bit 1: IEG1
Description
0
Falling edge of
IRQ
1
/TMIB pin input is detected
(initial value)
1
Rising edge of
IRQ
1
/TMIB pin input is detected
Bit 0—IRQ
0
Edge Select (IEG0):
Bit 0 selects the input sensing of pin
IRQ
0
.
Bit 0: IEG0
Description
0
Falling edge of
IRQ
0
pin input is detected
(initial value)
1
Rising edge of
IRQ
0
pin input is detected
Interrupt Enable Register 1 (IENR1)
Bit
7 6 5 4 3 2 1 0
IENTA
IENS1
*
IENWP IEN4
IEN3 IEN2
*
IEN1 IEN0
Initial
value 0 0 0 0 0 0 0 0
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W
Note:
*
Applies to the H8/3857 Group. In the H8/3854 Group, this bit must always be cleared to
0.
IENR1 is an 8-bit read/write register that enables or disables interrupt requests.
Summary of Contents for F-ZTAT H8 Series
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Page 194: ...7 RAM Rev 3 00 Jul 19 2007 page 168 of 532 REJ09B0397 0300...
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Page 274: ...9 Timers Rev 3 00 Jul 19 2007 page 248 of 532 REJ09B0397 0300...
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