3. Exception Handling
Rev.3.00 Jul. 19, 2007 page 78 of 532
REJ09B0397-0300
Interrupt Enable Register 2 (IENR2)
Bit
7 6 5 4 3 2 1 0
IENDT
IENAD
⎯
⎯
IENTFH
IENTFL
IENTC
*
IENTB
Initial
value 0 0 0 0 0 0 0 0
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W
Note:
*
Applies to the H8/3857 Group. In the H8/3854 Group, this bit must always be cleared to
0.
IENR2 is an 8-bit read/write register that enables or disables interrupt requests.
Bit 7—Direct Transfer Interrupt Enable (IENDT):
Bit 7 enables or disables direct transfer
interrupt requests.
Bit 7: IENDT
Description
0
Disables direct transfer interrupt requests
(initial value)
1
Enables direct transfer interrupt requests
Bit 6—A/D Converter Interrupt Enable (IENAD):
Bit 6 enables or disables A/D converter
interrupt requests.
Bit 6: IENAD
Description
0
Disables A/D converter interrupt requests
(initial value)
1
Enables A/D converter interrupt requests
Bits 5 and 4—Reserved Bits:
Bits 5 and 4 are reserved; they should always be cleared to 0.
Bit 3—Timer FH Interrupt Enable (IENTFH):
Bit 3 enables or disables timer FH compare
match and overflow interrupt requests.
Bit 3: IENTFH
Description
0
Disables timer FH interrupts
(initial value)
1
Enables timer FH interrupts
Summary of Contents for F-ZTAT H8 Series
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