10. Serial Communication Interface
Rev.3.00 Jul. 19, 2007 page 259 of 532
REJ09B0397-0300
When an external clock is used, data is transmitted and received in synchronization with the serial
clock input at pin SCK
1
. After data transmission and reception are complete, an overrun occurs if
the serial clock continues to be input; no data is transmitted or received and the SCSR1 overrun
error flag (bit ORER) is set to 1.
While transmission is stopped, the output value of pin SO
1
can be changed by rewriting bit SOL in
SCSR1.
10.2.4 Interrupts
SCI1 can generate an interrupt at the end of a data transfer.
When an SCI1 transfer is complete, bit IRRS1 in interrupt request register 1 (IRR1) is set to 1.
SCI1 interrupt requests can be enabled or disabled by bit IENS1 of interrupt enable register 1
(IENR1).
For further details, see section 3.3, Interrupts.
10.2.5 Application
Notes
Note the following points when using SCI1.
When an External Clock is Input to the SCK
1
Pin:
When SCK
1
is designated as an input
pin and an external clock is selected as the clock source, do not input the external clock before
writing 1 to the STF bit in SCSR1 to start the transfer operation.
Confirming the End of Serial Transfer:
Do not read or write to SCSR1 during serial
transfer. The following two methods can be used to confirm the end of serial transfer:
•
Using SCI1 interrupt exception handling
Set the IENS1 bit to 1 in IENR1 and execute interrupt exception handling.
•
Using IRR1 polling
With SCI1 interrupts disabled (IENS1 = 0 in IENR1), confirm that the IRRS1 bit in IRR1 has
been set to 1.
Summary of Contents for F-ZTAT H8 Series
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