10. Serial Communication Interface
Rev.3.00 Jul. 19, 2007 page 298 of 532
REJ09B0397-0300
Simultaneous Transmit/Receive:
Figure 10.19 shows a typical flow chart for transmitting and
receiving simultaneously. After SCI3 synchronization, follow the procedure below.
Start
Read bit TDRE in SSR
Read RDRF in SSR
RDRF = 1
?
Read received data in RDR
Read bit OER in SSR
OER = 1
?
Continue
transmitting and
receiving
?
Clear bits TE and
RE in SCR3 to 0
End
1
1.
2.
3.
4.
4
Read the serial status register (SSR),
and after confirming that bit TDRE = 1,
write transmit data in the transmit data
register (TDR). When data is written to
TDR, TDRE is automatically cleared to 0.
Read the serial status register (SSR),
and after confirming that bit RDRF = 1,
read the received data from the receive
data register (RDR). When data is read
from RDR, RDRF is automatically cleared
to 0.
To continue transmitting and receiving
serial data, read bit RDRF and finish
reading RDR before the MSB (bit 7) of the
present frame is received. Also read bit
TDRE and check that it is set to 1, indicating
that data can be written, then write the next
data in TDR, before the MSB (bit 7) of the
current frame is transmitted. When data is
written to TDR, TDRE is automatically cleared
to 0; and when data is read from RDR, RDRF
is automatically cleared to 0.
When an overrun error occurs, read bit
OER in SSR. After the necessary error
processing, be sure to clear OER to 0.
Data transmission and reception cannot
take place while bit OER is set to 1. See
figure 10.17 for overrun error processing.
TDRE = 1
?
No
No
Yes
Yes
Yes
No
3
No
Yes
Write transmit data in TDR
Overrun error processing
2
Figure 10.19 Simultaneous Transmit/Receive Flow Chart in Synchronous Mode
Summary of Contents for F-ZTAT H8 Series
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