9. Timers
Rev.3.00 Jul. 19, 2007 page 244 of 532
REJ09B0397-0300
Bit 4—Timer Control/Status Register W Write Enable (TCSRWE):
Bit 4 controls writing of
data to bits 2 and 0 of TCSRW.
Bit 4: TCSRWE Description
0
Writing to bits 2 and 0 is disabled
(initial valu
1
Writing to bits 2 and 0 is enabled
Bit 3—Bit 2 Write Inhibit (B2WI):
Bit 3 controls writing of data to bit 2 of TCSRW.
Bit 3: B2WI Description
0
Writing to bit 2 is enabled
1
Writing to bit 2 is disabled
(initial value)
This bit is always read as 1. Data is not stored if written to this bit.
Bit 2—Watchdog Timer On (WDON):
Bit 2 controls watchdog timer operation.
Bit 2: WDON Description
0
Watchdog timer operation is disabled
(initial value)
[Clearing condition]
In a reset, or when 0 is written to WDON while writing 0 to B2WI when TCSRWE = 1
1
Watchdog timer operation is enabled
[Setting condition]
When 1 is written to WDON while writing 0 to B2WI when TCSRWE = 1
The count-up starts when this bit is set to 1, and stops when it is cleared to 0.
Bit 1—Bit 0 Write Inhibit (B0WI):
Bit 1 controls writing of data to bit 0 of timer control/status
register W.
Bit 1: B0WI Description
0
Writing to bit 0 is enabled
1
Writing to bit 0 is disabled
(initial value)
This bit is always read as 1. Data is not stored if written to this bit.
Summary of Contents for F-ZTAT H8 Series
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