10. Serial Communication Interface
Rev.3.00 Jul. 19, 2007 page 270 of 532
REJ09B0397-0300
Serial Status Register (SSR)
Bit
7 6 5 4 3 2 1 0
TDRE
RDRF
OER
FER
PER
TEND
MPBR
MPBT
Initial
value 1 0 0 0 0 1 0 0
Read/Write R/(W)
*
R/(W)
*
R/(W)
*
R/(W)
*
R/(W)
*
R
R R/W
Note:
*
Only 0 can be written for flag clearing.
The serial status register (SSR) is an 8-bit register containing status flags for indicating SCI3
states, and containing the multiprocessor bits.
SSR can be read and written by the CPU at any time, but the CPU cannot write a 1 to the status
flags TDRE, RDRF, OER, PER, and FER. To clear these flags to 0 it is first necessary to read a 1.
Bit 2 (TEND) and bit 1 (MPBR) are read-only bits and cannot be modified.
SSR is initialized to H'84 upon reset or in standby mode, watch mode, subactive mode, or
subsleep mode.
Bit 7—Transmit Data Register Empty (TDRE):
Bit 7 is a status flag indicating that data has
been transferred from TDR to TSR.
Bit 7: TDRE
Description
0
Indicates that transmit data written to TDR has not been transferred to TSR
Clearing conditions:
After reading TDRE = 1, cleared by writing 0 to TDRE.
When data is written to TDR by an instruction.
1
Indicates that no transmit data has been written to TDR, or the transmit data
written to TDR has been transferred to TSR
(initial value)
Setting conditions:
When bit TE in SCR3 is cleared to 0.
When data is transferred from TDR to TSR.
Summary of Contents for F-ZTAT H8 Series
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