10. Serial Communication Interface
Rev.3.00 Jul. 19, 2007 page 274 of 532
REJ09B0397-0300
Bit Rate Register (BRR)
Bit
7 6 5 4 3 2 1 0
BRR7 BRR6 BRR5 BRR4 BRR3 BRR2 BRR1 BRR0
Initial
value 1 1 1 1 1 1 1 1
Read/Write R/W
R/W
R/W
R/W R/W R/W R/W R/W
The bit rate register (BRR) is an 8-bit register which, together with the baud rate generator clock
selected by bits CKS1 and CKS0 in the serial mode register (SMR), sets the transmit/receive bit
rate.
BRR can be read or written by the CPU at any time.
BRR is initialized to H'FF upon reset or in standby mode, watch mode, subactive mode, or
subsleep mode.
Table 10.6 gives examples of how BRR is set in asynchronous mode. The values in
table 10.6 are for active (high-speed) mode.
Table 10.6 BRR Settings and Bit Rates in Asynchronous Mode
OSC
(MHz)
2
2.4576
4
4.194304
Bit Rate
(bits/s)
n
N
Error
(
%
)
n
N
Error
(
%
)
n
N
Error
(
%
)
n
N
Error
(
%
)
110
1 70
+0.03
1 86
+0.31
1 141
+0.03
1 148
−
0.04
150
0 207
+0.16
0 255
0
1 103
+0.16
1 108
+0.21
300
0 103
+0.16
0 127
0
0 207
+0.16
0 217
+0.21
600
0 51
+0.16
0 63
0
0 103
+0.16
0 108
+0.21
1200
0 25
+0.16
0 31
0
0 51
+0.16
0 54
−
0.70
2400
0 12
+0.16
0 15
0
0 25
+0.16
0 26
+1.14
4800
⎯
⎯
⎯
0 7 0
0 12
+0.16
0 13
−
2.48
9600
⎯
⎯
⎯
0 3 0
⎯
⎯
⎯
0 6
−
2.48
19200
⎯
⎯
⎯
0 1 0
⎯
⎯
⎯
⎯
⎯
⎯
31250 0 0 0
⎯
⎯
⎯
0 1 0
⎯
⎯
⎯
38400
⎯
⎯
⎯
0 0 0
⎯
⎯
⎯
⎯
⎯
⎯
Summary of Contents for F-ZTAT H8 Series
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