Renesas F-ZTAT H8 Series, Hardware Manual

Page: 63 / 562

2. CPU
Rev.3.00 Jul. 19, 2007 page 37 of 532
REJ09B0397-0300
Table 2.2 Effective Address Calculation
No. Addressing Mode and
Instruction Format Effective Address
Calculation Method
Effective Address (EA)
1
Register direct, Rn
Operand is contents of
registers indicated by rm/rn
op rm rn
8 7 3 4 0 15
rm
3 0
rn
3 0
2
op rm
7 6 3 4 0 15
Register indirect, @Rn
Contents (16 bits) of
register indicated by rm
0 15
0 15
3 Register indirect with
displacement, @(d:16, Rn)
op rm
7 6 3 4 0 15
disp
0 15
disp
0 15
Contents (16 bits) of
register indicated by rm
4
op rm
7 6 3 4 0 15
Re g ister indirect with
post-increment, @Rn+
op rm
7 6 3 4 0 15
Re g ister indirect with
pre-decrement, @–Rn
Incremented or
decremented by 1 if
operand is byte size,
and by 2 if word size
0 15
1 or 2
0 15
0 15
1 or 2
0 15
Contents (16 bits) of
re g ister indicated by rm
Contents (16 bits) of
re g ister indicated by rm