6. ROM
Rev.3.00 Jul. 19, 2007 page 128 of 532
REJ09B0397-0300
Bit 2—Program-Verify (PV)
*
1
:
Bit 2 selects program-verify mode transition or clearing. (Do not
set the SWE, ESU, PSU, EV, E, or P bit at the same time.)
Bit 2: PV
Description
0
Program-verify mode cleared
(initial value)
1
Transition to program-verify mode
[Setting condition]
When FWE = 1 and SWE = 1
Bit 1—Erase (E)
*
1
*
3
:
Bit 1 selects erase mode transition or clearing. (Do not set the SWE, ESU,
PSU, EV, PV, or P bit at the same time.)
Bit 1: E
Description
0
Erase mode cleared
(initial value)
1
Transition to erase mode
[Setting condition]
When FWE = 1, SWE = 1, and ESU = 1
Bit 0—Program (P)
*
1
*
3
:
Bit 0 selects program mode transition or clearing. (Do not set the SWE,
ESU, PSU, EV, PV, or E bit at the same time.)
Bit 0: P
Description
0
Program mode cleared
(initial value)
1
Transition to program mode
[Setting condition]
When FWE = 1, SWE = 1, and PSU = 1
Notes: 1. Do not set multiple bits simultaneously. Do not cut V
CC
while a bit is set.
2. The SWE bit must not be set or cleared at the same time as other bits (bits EV, PV, E,
and P in FLMCR1, and bits ESU and PSU in FLMCR2).
3. P bit and E bit setting should be carried out in accordance with the program/erase
algorithms shown in section 6.5, Flash Memory Programming/Erasing. Before setting
either of these bits, a watchdog timer setting should be made to prevent program
runaway. See section 6.9, Flash Memory Programming and Erasing Precautions, for
more information on the use of these bits.
Summary of Contents for F-ZTAT H8 Series
Page 6: ...Rev 3 00 Jul 19 2007 page iv of xxiv REJ09B0397 0300...
Page 194: ...7 RAM Rev 3 00 Jul 19 2007 page 168 of 532 REJ09B0397 0300...
Page 234: ...8 I O Ports Rev 3 00 Jul 19 2007 page 208 of 532 REJ09B0397 0300...
Page 274: ...9 Timers Rev 3 00 Jul 19 2007 page 248 of 532 REJ09B0397 0300...
Page 352: ...12 A D Converter Rev 3 00 Jul 19 2007 page 326 of 532 REJ09B0397 0300...
Page 561: ......
