Renesas F-ZTAT H8 Series, Hardware Manual

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3. Exception Handling
Rev.3.00 Jul. 19, 2007 page 75 of 532
REJ09B0397-0300
3.3.2 Interrupt Control Registers
Table 3.3 lists the registers that control interrupts.
Table 3.3 Interrupt Control Registers
Register Name Abbreviation R/W Initial Value Address
IRQ edge select register *
2
IEGR R/W H'E0 H'FFF2
Interrupt enable register 1 *
2
IENR1 R/W H'00 H'FFF3
Interrupt enable register 2
*
2
IENR2 R/W H'00 H'FFF4
Interrupt request register 1 *
2
IRR1 R/W *
1
H'20 H'FFF6
Interrupt request register 2 *
2
IRR2 R/W *
1
H'00 H'FFF7
Wakeup interrupt request register IWPR R/W *
1
H'00 H'FFF9
Notes: 1. Write is enabled only for writing of 0 to clear a flag.
2. There are some differences in functions between the H8/3857 Group and the H8/3854
Group. For details, see the individual register descriptions.
IRQ Edge Select Register (IEGR)
Bit 7 6 5 4 3 2 1 0
⎯ ⎯ ⎯
IEG4 IEG3 IEG2
*
IEG1 IEG0
Initial value 1 1 1 0 0 0 0 0
Read/Write
⎯ ⎯ ⎯
R/W R/W R/W R/W R/W
Note: * Applies to the H8/3857 Group. In the H8/3854 Group, this bit must always be cleared to
0.
IEGR is an 8-bit read/write register, used to designate whether pins
IRQ
0
to
IRQ
4
are set to rising
edge sensing or falling edge sensing.
Bits 7 to 5—Reserved Bits: Bits 7 to 5 are reserved; they are always read as 1, and cannot be
modified.
Bit 4—IRQ
4
Edge Select (IEG4): Bit 4 selects the input sensing of pin
IRQ
4
/
ADTRG
.
Bit 4: IEG4 Description
0 Falling edge of
IRQ
4
/
ADTRG
pin input is detected (initial value)
1 Rising edge of
IRQ
4
/
ADTRG
pin input is detected