Omron CJ1G-CPUxx, Instructions Manual

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Timer and Counter Instructions Section 3-6
Timers Created with Timer Numbers 0000 to 2047
Timers Created with Timer Numbers 2048 to 4095
Timers are reset (PV = SV, Completion Flag OFF) by power interruptions
unless the IOM Hold Bit (A50012) is ON and the bit is protected in the PLC
Setup. It is also possible use a clock pulse bit and a counter instruction to pro-
gram a timer that will retain its PV in the event of a power interruption, as
shown in the following diagram.
Example When timer input CIO 000000 goes from OFF to ON in the following example,
the timer PV will begin counting down from the SV. Timer Completion Flag
T0000 will be turned ON when the PV reaches 0000.
When CIO 000000 goes OFF, the timer PV will be reset to the SV and the
Completion Flag will be turned OFF.
3-6-2 HIGH-SPEED TIMER: TIMH(015)/TIMHX(551)
Purpose TIMH(015)/TIMHX(551) operates a decrementing timer with units of 10-ms.
The setting range for the set value (SV) is 0 to 99.99 s for TIMH(015) and 0 to
655.35 s for TIMHX(551). The timer accuracy is 0 to 0.01 s.
Note The timer accuracy for CS1D CPU Units is 10 ms + the cycle time
Execution of TIM/
TIMX(550) The PV is updated every time that TIM/TIMX(550) is exe-
cuted.
The Completion Flag is turned ON if the PV is 0000.
The Completion Flag is turned OFF if the PV isn’t 0000.
After executing all tasks The PV is also updated every cycle at the end of pro-
gram execution.
80-ms interval refreshing If the cycle time exceeds 80 ms, the timer’s PV is
updated every 80 ms.
Execution of TIM The PV is updated every time that TIM is executed.
The Completion Flag is turned ON if the PV is 0000.
The Completion Flag is turned OFF if the PV isn’t 0000.
Execution
condition
1-s clock
pulse bit
Count input
Reset input
Timer input
CIO 000000
Timer PV
T0000
Timer
Completion
Flag
T0000