Omron CJ1G-CPUxx, Instructions Manual

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1057
CS-series Instruction Execution Times and Number of Steps Section 4-1
Note 1. When a double-length operand is used, add 1 to the value shown in the
length column in the following table.
2. Immediate refreshing is not supported by the CS1D CPU Units.
3. Not supported by the CS1D CPU Units.
4-1-2 Sequence Output Instructions
Instruction Mnemonic Code Length
(steps)
(See note.)
ON execution time (
µ
s) Conditions
CPU6 @ H CPU4 @ H CPU6 @ CPU4 @
OUTPUT OUT --- 1 0.02 0.04 0.17 0.21 ---
!OUT (See
note 2.) --- 2 +21.37 +21.37 +21.37 +21.37 Increase for CS
Series
+49.3 +49.3 +49.3 +49.3 Increase for
C200H
(See note 3.)
OUTPUT NOT OUT NOT --- 1 0.02 0.04 0.17 0.21 ---
!OUT NOT
(See note
2.) --- 2 +21.37 +21.37 +21.37 +21.37 Increase for CS
Series
+49.3 +49.3 +49.3 +49.3 Increase for
C200H
(See note 3.)
KEEP KEEP 011 1 0.06 0.08 0.25 0.29 ---
DIFFERENTI-
ATE UP DIFU 013 2 0.24 0.40 0.46 0.54 ---
DIFFERENTI-
ATE DOWN DIFD 014 2 0.24 0.40 0.46 0.54 ---
SET SET --- 1 0.02 0.06 0.17 0.21 ---
!SET (See
note 2.) --- 2 +21.37 +21.37 +21.37 +21.37 Increase for CS
Series
+49.3 +49.3 +49.3 +49.3 Increase for
C200H
(See note 3.)
RESET RSET --- 1 0.02 0.06 0.17 0.21 Word specified
!RSET
(See note
2.) --- 2 +21.37 +21.37 +21.37 +21.37 Increase for CS
Series
+49.3 +49.3 +49.3 +49.3 Increase for
C200H
(See note 3.)
MULTIPLE
BIT SET SETA 530 4 5.8 6.1 7.8 7.8 With 1-bit set
25.7 27.2 38.8 38.8 With 1,000-bit
set
MULTIPLE
BIT RESET RSTA 531 4 5.7 6.1 7.8 7.8 With 1-bit reset
25.8 27.1 38.8 38.8 With 1,000-bit
reset
SINGLE BIT
SET SETB 532 2 0.24 0.34 --- --- ---
!SETB (See
note 2.) 3 +21.44 +21.54 --- --- ---
SINGLE BIT
RESET RSTB 534 2 0.24 0.34 --- --- ---
!RSTB
(See note
2.) 3 +21.44 +21.54 --- --- ---
SINGLE BIT
OUTPUT OUTB 534 2 0.22 0.32 --- --- ---
!OUTB
(See note
2.) 3 +21.42 +21.52 --- --- ---