DDR2(+LP) Compliance Testing Methods of Implementation
207
Clock Timing (CT) Tests
14
Measurement Algorithm
1 Acquire and split read and write burst of the acquired signal. (See notes on DDR read/write
separation).
2 Gather all tDQSCKm value in all valid READ bursts found in acquisition. Here is the
sub-procedure to measure tDQSCKm value.
3 Evaluate all the sub-burst in the current burst by checking with Chip Select signal.
4 Find all DQS middle cross point at V
REF
in the said burst. (See notes on threshold).
5 Find all Clock middle cross point at V
REF
in the said burst. (See notes on threshold).
6 For sub-burst # 1, find the first DQS rising edge by search the earliest rising cross point among all
found DQS middle cross point within current sub-burst. Take the found point (first DQS rising
edge) as tDQSCKm strobe point.
7 Find the closest Clock - DQS : the Clock rising middle cross point that closest to first DQS rising
edge.
8 Find tDQSCKm clock point which clock middle crosspoint that before closest Clock - DQS at
tDQSCK Delay (cycle). By default, tDQSCK Delay is one cycle. In example, for tDQSCK Delay = 1,
tDQSCKm clock point is clock middle crosspoint that previous of closest Clock - DQS. For
tDQSCK Delay = 3, tDQSCKm clock point is clock middle crosspoint that three clock before with
closest Clock - DQS. tDQSCK Delay is configurable in configuration page.
9 Compare these tDQSCKm strobe point to tDQSCKm clock point as a tDQSCKm value.
Mathematically,
tDQSCKm = tDQSCKm strobe point - tDQSCKm clock point
.
10 Repeat procedure (
6
) to (
9
) for the rest of sub-burst in the current burst.
11 Perform checking of tDQSCKm #1 value with tDQSCKm #2 value. If the distance of clock
reference of these two measured tDQSCKm is within 1.6 μs, then compare tDQSCKm #1 value
and tDQSCKm #2 value. Mathematically, tDQSCKDS #1 = |tDQSCKm #1 - tDQSCKm #2|.
Otherwise, if the distance of clock reference of these two measured tDQSCKm is more than 1.6
μs, disregard to perform any comparison. Perform this procedure to all possible cross check of
gathered tDQSCKm.
12 The largest tDQSCKDM value found will be taken as test result.
13 Display the test result by spot to measurement location on waveform and locate the marker to
tDQSCKm strobe point and tDQSCKm clock point for pair of worst tDQSCKm.
14 Compare test result to compliance test limit.
Summary of Contents for D9020DDRC
Page 1: ...Keysight D9020DDRC DDR2 LP Compliance Test Application Methods of Implementation ...
Page 10: ...10 DDR2 LP Compliance Testing Methods of Implementation ...
Page 46: ...2 Preparing to Take Measurements 30 DDR2 LP Compliance Testing Methods of Implementation ...
Page 70: ...3 Measurement Clock Tests 54 DDR2 LP Compliance Testing Methods of Implementation ...
Page 224: ...14 Clock Timing CT Tests 208 DDR2 LP Compliance Testing Methods of Implementation ...
Page 270: ...15 Data Strobe Timing DST Tests 254 DDR2 LP Compliance Testing Methods of Implementation ...