4
Single-Ended Signals AC Input Parameters Tests
74
DDR2(+LP) Compliance Testing Methods of Implementation
V
IL(AC)
Test for Address, Control - Test Method of Implementation
V
IL(AC)
- Minimum AC Input Logic Low Address, Control.
The purpose of this test is to verify that the mode low level voltage value of the histogram for the test
signal is lower than the conformance maximum limits of the V
IL(AC)
value specified in the JEDEC
specification.
The value of V
REF
which directly affects the conformance lower limit is set to 0.9V. User may choose
to use the UDL (User Defined Limit) feature in the application to perform this test against a
customized test limit set based on the different values of V
REF
.
The value of V
PEAK
which directly affects the conformance upper limit is set to 0.5V. User may choose
to use the UDL (User Defined Limit) feature in the application to perform this test against a
customized test limit set based on the different values of V
PEAK
.
The value of V
DDQ
which directly affects the conformance upper limit is set to 1.8V. User may choose
to use the UDL (User Defined Limit) feature in the application to perform this test against a
customized test limit set based on the different values of V
DDQ
.
The value of V
SSQ
which directly affect the conformance upper limit is set to 0V. User may choose to
use the UDL (User Defined Limit) feature in the application to perform this test against a customize
test limit set based on different values of V
SSQ
.
Signals of Interest
Mode Supported: DDR2 only
Signal cycle of interest: WRITE
Required Read/Write separation: No
Signal(s) of Interest:
• Address Signal OR
• Control Signal OR
• Clock Signal
Signals required to perform the test on the oscilloscope:
• Pin Under Test, PUT - any signal of interest, as defined above
Test Definition Notes from the Specification
Table 43
Input AC Logic Level
Symbol
Parameter
DDR2-400, DDR2-533
DDR2-667, DDR2-800
Units
Notes
Min
Max
Min
Max
V
IL(AC)
AC input logic LOW
V
SSQ
-V
PEAK
V
REF
- 0.250
V
SSQ
-V
PEAK
V
REF
- 0.200
V
1
Table 44
Input AC Logic Level (DDR2-1066)
Symbol
Parameter
DDR2-1066
Units
Notes
Min
Max
V
IL(AC)
AC input logic LOW
-
V
REF
- 0.200
V
-
Summary of Contents for D9020DDRC
Page 1: ...Keysight D9020DDRC DDR2 LP Compliance Test Application Methods of Implementation ...
Page 10: ...10 DDR2 LP Compliance Testing Methods of Implementation ...
Page 46: ...2 Preparing to Take Measurements 30 DDR2 LP Compliance Testing Methods of Implementation ...
Page 70: ...3 Measurement Clock Tests 54 DDR2 LP Compliance Testing Methods of Implementation ...
Page 224: ...14 Clock Timing CT Tests 208 DDR2 LP Compliance Testing Methods of Implementation ...
Page 270: ...15 Data Strobe Timing DST Tests 254 DDR2 LP Compliance Testing Methods of Implementation ...