Keysight Technologies D9020DDRC, Manual

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4 Single-Ended Signals AC Input Parameters Tests
70 DDR2(+LP) Compliance Testing Methods of Implementation
V
IL(AC)
Test for DQ, DM - Test Method of Implementation
V
IL(AC)
- Minimum AC Input Logic Low for DQ, DM.
The purpose of this test is to verify that voltage level of test signal at tDS (DM and DQ input setup
time in JEDEC specification) before DQS midpoint is lower than the conformance maximum limits of
the V
IL(AC)
value specified in the JEDEC specification.
The value of V
REF
which directly affects the conformance lower limit is set to 0.9V. User may choose
to use the UDL (User Defined Limit) feature in the application to perform this test against a
customized test limit set based on the different values of V
REF
.
The value of V
PEAK
which directly affects the conformance upper limit is set to 0.5V. User may choose
to use the UDL (User Defined Limit) feature in the application to perform this test against a
customized test limit set based on the different values of V
PEAK
.
The value of V
DDQ
which directly affects the conformance upper limit is set to 1.8V. User may choose
to use the UDL (User Defined Limit) feature in the application to perform this test against a
customized test limit set based on the different values of V
DDQ
.
The value of V
SSQ
which directly affect the conformance upper limit is set to 0V. User may choose to
use the UDL (User Defined Limit) feature in the application to perform this test against a customize
test limit set based on different values of V
SSQ
.
Signals of Interest
Mode Supported: DDR2 only
Signal cycle of interest: WRITE
Required Read/Write separation: Yes
Signal(s) of Interest:
• Data Signal (supported by Data Strobe Signal) OR
• Data Mask Signal (supported by Data Strobe Signal)
Signals required to perform the test on the oscilloscope:
• Pin Under Test, PUT - any signal of interest, as defined above
• Supporting Pin - Data Strobe Signals
Test Definition Notes from the Specification
Table 39 Input AC Logic Level
Symbol Parameter DDR2-400, DDR2-533 DDR2-667, DDR2-800 Units Notes
Min Max Min Max
V
IL(AC)
AC input logic LOW V
SSQ
-V
PEAK
V
REF
- 0.250 V
SSQ
-V
PEAK
V
REF
- 0.200 V 1
Table 40 Input AC Logic Level (DDR2-1066)
Symbol Parameter DDR2-1066 Units Notes
Min Max
V
IL(AC)
AC input logic LOW - V
REF
- 0.200 V -