Keysight Technologies D9020DDRC, Manual

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15 Data Strobe Timing (DST) Tests
248 DDR2(+LP) Compliance Testing Methods of Implementation
tQSH, DQS Output High Pulse Width - Test Method of Implementation
The purpose of this test is to verify that the width of the high level of the Data Strobe signal is within
the conformance limit as specified in the JEDEC specification.
Signals of Interest
Mode Supported: LPDDR2 only
Signal cycle of interest: READ
Signal(s) of Interest:
• Data Strobe Signal (supported by Data Signal)
Optional signal(s):
• Chip Select Signal (this signal is used to separate DQS signals from different rank of memory)
Signals required to perform the test on the oscilloscope:
• Data Signal, DQ
• Data Strobe Signal, DQS
• Chip Select Signal, CS (optional)
Test Definition Notes from the Specification
Test References
See Table 103 - LPDDR2 AC Timing Table in the JESD209-2B .
PASS Condition
The worst measured tQSH shall be within the specification limit.
Measurement Algorithm
1 Acquire and split read and write burst of the acquired signal.
2 Take the first valid READ burst found.
3 Find all valid rising and falling DQS crossing in this burst.
4 tQSH is the time interval starting from a rising edge of the DQS and ending at the following
falling edge.
5 Collect all tQSH.
6 Determine the worst result from the measured tQSH.
Table 168 LPDDR2 AC Timing Table
Parameter Symbol Min
Max Min
t
CK
LPDDR2 Unit
1066 933 800 677 533 466*
5
400 333 266*
5
200*
5
Read Parameters*
14
DQS output high
pulse width
tQSH Min
t
CH
(abs) - 0.05 t
CK
(avg)