Keysight Technologies D9020DDRC, Manual

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5 Single-Ended Signals VIH/VIL (Address, Control) Tests
104 DDR2(+LP) Compliance Testing Methods of Implementation
V
IHCA(DC)
- Test Method of Implementation
V
IHCA(DC)
- DC Input Logic HIGH (Address, Control).
The purpose of this test is to verify that the histogram mode high level voltage value of the test signal
within a valid sampling window is greater than the conformance lower limits of the V
IHCA(DC)
value
specified in the JEDEC specification.
The value of V
REF
(which directly affects the conformance lower limit) is set to 0.6V for the
compliance limit set used. You may choose to use the User Defined Limit feature in the application to
perform this test against a customized test limit set based on different values of V
REF
.
The value of V
DDCA
(which directly affects the conformance lower limit) is set to 1.2V for the
compliance limit set used. You may choose to use the User Defined Limit feature in the application to
perform this test against a customized test limit set based on different values of V
DDCA
.
Signals of Interest
Mode Supported: LPDDR2 only
Signal cycle of interest: WRITE
Signal(s) of Interest:
• Command/Address Signals
• Chip Select Signals
Signals required to perform the test on the oscilloscope:
• Pin Under Test, PUT - any signal of interest, as defined above.
Test Definition Notes from the Specification
Test References
See Table 74 - Single-ended AC and DC Input Levels for CA and CS_n Inputs in the JESD209-2B .
PASS Condition
The mode value for the high level voltage must be greater than or equal to the minimum V
IHCA(DC)
value.
Measurement Algorithm
1 Sample/acquire signal data.
2 Find all valid positive pulses. A valid positive pulse starts at V
REF
crossing at valid rising edge and
end at V
REF
crossing at the following valid falling edge (See notes on threshold).
3 Zoom in on the first valid positive pulse and perform V
TOP
measurement. Take the V
TOP
measurement results as V
IHCA(DC)
value.
4 Continue the previous step with another nine valid positive pulses.
5 Determine the worst result from the set of V
IHCA(DC)
measured.
Table 68 Single-ended AC and DC Input Levels for CA and CS_n Inputs
Symbol Parameter LPDDR2-1066 to LPDDR2-466 LPDDR2-400 to LPDDR2-200 Units Notes
Min Max Min Max
V
IHCA(DC)
DC input logic HIGH V
REF
+ 0.130 V
DDCA
V
REF
+ 0.200 V
DDCA
V 1